公开(公告)号：US11605441B1

公开(公告)日：2023-03-14

申请号：US17461380

申请日：2021-08-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunghye Cho ,  Kiheung Kim ,  Sungrae Kim ,  Junhyung Kim ,  Kijun Lee ,  Myungkyu Lee ,  Changyong Lee ,  Sanguhn Cha

IPC: G11C29/42 ,  G11C29/44 ,  G11C11/408 ,  G11C11/4091 ,  G11C29/12

Abstract: A memory system includes a memory module having a plurality of memory devices therein. A memory controller is configured to transmit commands and addresses to the memory module in synchronization with a clock, input/output data to and from the memory module in synchronization with a data transfer clock, and perform system error correction operations on data read from the memory module. The plurality of memory devices perform on-die error correction operations, which are different from each other according to a physical location of the stored read data.

公开(公告)号：US20230004308A1

公开(公告)日：2023-01-05

申请号：US17704354

申请日：2022-03-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungrae Kim ,  Sunghye Cho ,  Kijun Lee ,  Myungkyu Lee

IPC: G06F3/06

Abstract: In a method of operating a memory controller, a decoding status flag is received from a memory module including a plurality of data chips and at least one parity chip. Each of the plurality of data chips and the at least one parity chip may include an on-die error correction code (ECC) engine. The decoding status flag is generated by the on-die ECC engines. A first number and a second number may be obtained based on the decoding status flag. The first number represents a number of first chips including an uncorrectable error that is uncorrectable by the on-die ECC engine. The second number represents a number of second chips including a correctable error that is correctable by the on-die ECC engine. At least one of a plurality of decoding schemes is selected based on at least one of the first number and the second number. A system ECC engine may perform ECC decoding on at least one of the first chips and the second chips based on the selected decoding scheme.

公开(公告)号：US11314592B2

公开(公告)日：2022-04-26

申请号：US16909730

申请日：2020-06-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeonggeol Song ,  Sungrae Kim ,  Kijun Lee

IPC: G06F11/10 ,  G11C29/52 ,  G11C11/4091 ,  G11C11/56 ,  G11C11/4093 ,  H01L25/065

Abstract: A semiconductor memory device includes a memory cell array, an error correction circuit and a control logic circuit. The error correction circuit includes an error correction code (ECC) decoder to perform an ECC decoding on a codeword including a main data and a parity data, read from a target page of the memory cell array to correct errors in the read codeword. The control logic circuit controls the error correction circuit based on a command and address from an external memory controller. The ECC decoder has t-bit error correction capability, generates a syndrome based on the codeword using a parity check matrix, performs t iterations during (t−2) cycles to generate an error locator polynomial based on the syndrome, searches error positions in the codeword based on the error locator polynomial and corrects the errors in the codeword based on the searched error positions.

公开(公告)号：US20210194508A1

公开(公告)日：2021-06-24

申请号：US16987554

申请日：2020-08-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungrae Kim ,  Kijun Lee ,  Myungkyu Lee ,  Sunghye Cho ,  Chanki Kim ,  Yeonggeol Song

IPC: H03M13/15 ,  H03M13/11 ,  G06F11/10 ,  G06F9/30

Abstract: A memory controller includes an error correction circuit and a central processing unit (CPU) to control the error correction circuit. The error correction circuit includes an error correction code (ECC) decoder and a memory to store a parity check matrix. The ECC decoder performs an ECC decoding on a codeword read from the memory module to: (i) generate a first syndrome and a second syndrome, (ii) generate a decoding mode flag associated with a type of errors in the codeword based on the second syndrome and a decision syndrome, (iii) operate in one of a first decoding mode and a second decoding mode based on the decoding mode flag, and (iv) selectively correct one of a chip error associated with one of the data chips and one or more symbol errors in the codeword.

公开(公告)号：US12170533B2

公开(公告)日：2024-12-17

申请号：US18336285

申请日：2023-06-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungrae Kim ,  Gilyoung Kang ,  Yujung Song ,  Hyeran Kim ,  Chisung Oh

IPC: H03M13/29 ,  G06F3/06 ,  G06F11/10 ,  G11C11/4096 ,  G11C29/42 ,  G11C29/52 ,  H03M13/15

Abstract: A semiconductor memory device includes a memory cell array and an on-die error correction code (ECC) engine. The on-die ECC engine, during a write operation, generates a second main data by encoding a first main data with a random binary code, performs an ECC encoding on the second main data to generate a parity data and stores the second main data and the parity data in a target page in the memory cell array. The on-die ECC engine, during a read operation, reads the second main data and the parity data from the target page, performs an ECC decoding on the second main data based on the parity data to generate a syndrome in parallel with generating the first main data by encoding the second main data with the random binary code and corrects at least one error bit in the first main data based on the syndrome.

公开(公告)号：US12066893B2

公开(公告)日：2024-08-20

申请号：US18226622

申请日：2023-07-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungrae Kim ,  Kijun Lee ,  Myungkyu Lee ,  Yeonggeol Song ,  Jinhoon Jang ,  Sunghye Cho ,  Isak Hwang

IPC: G06F11/10 ,  G06F11/07 ,  G06F11/30 ,  G06F13/16 ,  G06F13/28

CPC classification number: G06F11/1068

Abstract: A semiconductor memory device includes a memory cell array, a link error correction code (ECC) engine and on-die ECC engine. The memory cell array includes a plurality of volatile memory cells. The link ECC engine provides a main data by performing a first ECC decoding on a first codeword including the main data and a first parity data, and generates a first error flag based on a result of the first ECC decoding. The on-die ECC engine generates a second parity data by performing a first ECC encoding on the main data, provides a target page of the memory cell array with a second codeword including the main data and the second parity data in response to the first error flag being deactivated or generates a third codeword by changing at least one of bits of the second codeword in response to the first error flag being deactivated.

公开(公告)号：US11942968B2

公开(公告)日：2024-03-26

申请号：US17975034

申请日：2022-10-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changkyu Seol ,  Sungrae Kim ,  Chisung Oh ,  Junghwan Choi

IPC: H03M13/00 ,  H03M5/14 ,  H04L1/00

CPC classification number: H03M5/145 ,  H04L1/0009 ,  H04L1/0014

Abstract: A transmitter includes an encoder configured to divide a first number of binary input bits of an input data signal into a first bit group and a second bit group, generate a first intermediate bit group and a second intermediate bit group by manipulating the first bit group and the second bit group differently based on a value of the first bit group, and generate a first symbol group and a second symbol group by encoding the first intermediate bit group and the second intermediate bit group, each of the first symbol group and the second symbol group including a plurality of symbols, and each of the plurality of symbols having three different voltage levels. The transmitter includes a driver configured to generate an output data signal by concatenating the first symbol group and the second symbol group.

公开(公告)号：US20240029808A1

公开(公告)日：2024-01-25

申请号：US18174186

申请日：2023-02-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yujung Song ,  Sungrae Kim ,  Gilyoung Kang ,  Hyeran Kim ,  Chisung Oh

IPC: G11C29/42 ,  G11C29/46 ,  G11C29/12

CPC classification number: G11C29/42 ,  G11C29/46 ,  G11C29/1201

Abstract: A semiconductor memory device includes a memory cell array, an on-die error correction code (ECC) engine and a control logic circuit. The on-die ECC engine includes a first latch and a second latch. The control logic circuit sets the semiconductor memory device to a test mode in response to a first mode register set command. The on-die ECC engine, in the test mode, cuts off a connection with the memory cell array, receives a test data, stores the test data in the first latch, performs an ECC decoding on the test data stored in the first latch and a test parity data, stored in the second latch in response to a read command and provides an external device with a severity signal indicating whether the test data and the test parity data includes at least one error bit and the at least one error bit is correctable.

公开(公告)号：US20230377669A1

公开(公告)日：2023-11-23

申请号：US18134776

申请日：2023-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonyoung Choi ,  Gilyoung Kang ,  Sungrae Kim ,  Hyeran Kim ,  Jeongseok Park ,  Changkyu Seol

IPC: G11C29/36 ,  G11C29/14 ,  G11C29/38

CPC classification number: G11C29/36 ,  G11C29/14 ,  G11C29/38

Abstract: A memory device, an operating method of the memory device, and a test system including the memory device. The memory device may include a decoder group configured to receive a plurality of codewords including a plurality of symbols from outside of the memory device and to decode the plurality of codewords into data patterns, a memory cell array configured to store the data patterns received from the decoder group and including a plurality of memory cells, and an encoder configured to encode the data patterns into the plurality of codewords including the plurality of symbols. The plurality of codewords may include illegal codewords and normal codewords, and the decoder group may be further configured to convert the illegal codewords among the plurality of codewords into fixed patterns, and the encoder may be configured to output the plurality of codewords to the outside of the memory device.

公开(公告)号：US11762736B2

公开(公告)日：2023-09-19

申请号：US17580048

申请日：2022-01-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungrae Kim ,  Kijun Lee ,  Myungkyu Lee ,  Yeonggeol Song ,  Jinhoon Jang ,  Sunghye Cho ,  Isak Hwang

IPC: G06F11/10 ,  G06F11/07 ,  G06F13/28 ,  G06F13/16 ,  G06F11/30

CPC classification number: G06F11/1068

Abstract: A semiconductor memory device includes a memory cell array, a link error correction code (ECC) engine and on-die ECC engine. The memory cell array includes a plurality of volatile memory cells. The link ECC engine provides a main data by performing a first ECC decoding on a first codeword including the main data and a first parity data, and generates a first error flag based on a result of the first ECC decoding. The on-die ECC engine generates a second parity data by performing a first ECC encoding on the main data, provides a target page of the memory cell array with a second codeword including the main data and the second parity data in response to the first error flag being deactivated or generates a third codeword by changing at least one of bits of the second codeword in response to the first error flag being deactivated.