公开(公告)号：US12218102B2

公开(公告)日：2025-02-04

申请号：US17728727

申请日：2022-04-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngkun Jee ,  Unbyoung Kang ,  Sanghoon Lee ,  Chungsun Lee

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48

Abstract: A semiconductor package includes a first semiconductor chip including a first semiconductor substrate, and a plurality of first through electrodes penetrating at least a portion of the first semiconductor substrate. A plurality of second semiconductors include a second semiconductor substrate, the plurality of second semiconductor chips being stacked on the first semiconductor chip. A plurality of bonding pads are arranged between the first semiconductor chip and the plurality of second semiconductor chips. A chip bonding insulating layer is arranged between the first semiconductor chip and the plurality of second semiconductor chips. At least one supporting dummy substrate is stacked on the plurality of second semiconductor chips and having a support bonding insulating layer arranged on a lower surface thereof.

公开(公告)号：US20240387463A1

公开(公告)日：2024-11-21

申请号：US18614964

申请日：2024-03-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeonggi Jin ,  Gyuho Kang ,  Unbyoung Kang ,  Taehee Kim ,  Hyungjun Park

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/10 ,  H01L23/31 ,  H01L23/498 ,  H01L25/10

Abstract: A semiconductor package includes a semiconductor device including a substrate, bonding pads provided on a front surface of the substrate and bump structures provided on the bonding pads respectively, each of the bump structures having a metal pillar and a metal paste coated on one end portion of the metal pillar; and a wiring layer including a metal wiring layer having redistribution pads and a protective layer on the metal wiring layer and having recesses that expose at least portions of the redistribution pads. The semiconductor device is stacked on the wiring layer via the bump structures. Portions of the bump structures are respectively disposed in the recesses of the protective layer, and the metal pastes are respectively bonded to the redistribution pads.

公开(公告)号：US20240321700A1

公开(公告)日：2024-09-26

申请号：US18612492

申请日：2024-03-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daeyeun Choi ,  Taeho Ko ,  Unbyoung Kang ,  Seokbong Park

IPC: H01L23/498 ,  H01L21/52 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L25/10 ,  H10B80/00

CPC classification number: H01L23/49811 ,  H01L21/52 ,  H01L21/56 ,  H01L23/3107 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/81 ,  H01L25/105 ,  H10B80/00 ,  H01L2224/16227 ,  H01L2224/19 ,  H01L2224/2101 ,  H01L2224/22 ,  H01L2224/81

Abstract: A semiconductor package includes an upper redistribution structure, a first substrate, a first semiconductor chip, a second semiconductor chip, a bridge chip, and a first insulating layer. The upper redistribution structure includes an upper redistribution insulating layer and upper redistribution patterns. The first substrate includes an upper surface, a lower surface, a first cavity extending in a vertical direction, and a second cavity provided apart from the first cavity in a horizontal direction and extending in the vertical direction. The first substrate is on an upper surface of the upper redistribution structure. The first semiconductor chip is accommodated in the first cavity and electrically connected to a subset of the upper redistribution patterns. The second semiconductor chip is accommodated in the second cavity and electrically connected to a subset of the upper redistribution patterns. The bridge chip is below the upper redistribution structure. The first insulating layer surrounds the bridge chip.

公开(公告)号：US20240213174A1

公开(公告)日：2024-06-27

申请号：US18515797

申请日：2023-11-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junghoon Kang ,  Unbyoung Kang ,  Jinsu Kim ,  Seungwan Shin ,  Byoungwook Jang

IPC: H01L23/544 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L25/10

CPC classification number: H01L23/544 ,  H01L23/3128 ,  H01L23/49811 ,  H01L24/16 ,  H01L24/20 ,  H01L25/0657 ,  H01L25/105 ,  H01L2223/54433 ,  H01L2224/16225 ,  H01L2224/21 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562

Abstract: A semiconductor package includes a lower redistribution wiring layer having a first region and a second region adjacent the first region and including first redistribution wirings; a semiconductor chip on the first region of the lower redistribution wiring layer and electrically connected to the first redistribution wirings; a sealing member on a side surface of the semiconductor chip and on the lower redistribution wiring layer; a plurality of vertical conductive structures penetrating the sealing member on the second region of the lower redistribution wiring layer and electrically connected to the first redistribution wirings; a marking pattern on the semiconductor chip; seed layer pads on respective end portions of the vertical conductive structures that are exposed by the sealing member at an upper surface thereof; and an upper redistribution wiring layer on the sealing member and the marking pattern and including second redistribution wirings.

公开(公告)号：US20240186289A1

公开(公告)日：2024-06-06

申请号：US18226990

申请日：2023-07-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hanmin Lee ,  Unbyoung Kang ,  Seongyo Kim ,  Sangsick Park

IPC: H01L25/065 ,  H01L21/461 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H10B80/00

CPC classification number: H01L25/0657 ,  H01L21/461 ,  H01L21/563 ,  H01L23/3114 ,  H01L24/16 ,  H01L24/32 ,  H01L25/50 ,  H10B80/00 ,  H01L2224/16145 ,  H01L2224/32145

Abstract: A method of manufacturing a semiconductor package comprises stacking, via an adhesive member, a plurality of memory dies to form a memory die stack on a buffer die; forming a first molding member on the buffer die to cover the memory die stack; polishing an upper surface of the first molding member to expose an upper surface of an uppermost memory die in the memory die stack, the uppermost memory die positioned in an uppermost layer in the memory die stack; removing edge portions of the uppermost memory die together with at least a portion of the first molding member and at least a portion of the adhesive member to form a stepped portion; and forming a second molding member on the first molding member to cover the stepped portion of the uppermost memory die.

公开(公告)号：US11967581B2

公开(公告)日：2024-04-23

申请号：US18110446

申请日：2023-02-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinwoo Park ,  Unbyoung Kang ,  Jongho Lee ,  Teakhoon Lee

IPC: H01L23/16 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L25/065

CPC classification number: H01L25/0652 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3675 ,  H01L23/562 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2225/06589

Abstract: A package structure includes a lower substrate, substrate connection terminals on the lower substrate, a semiconductor package on the substrate connection terminals, the semiconductor package including a package substrate and a first encapsulant covering the package substrate, first underfills between the lower substrate and the semiconductor package, the first underfills covering corner portions of the semiconductor package, as viewed in a plan view, and covering at least one of the substrate connection terminals, and a second underfill between the lower substrate and the semiconductor package, the second underfill covering a side surface of the semiconductor package in a plan view.

公开(公告)号：US20240096851A1

公开(公告)日：2024-03-21

申请号：US18301403

申请日：2023-04-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Unbyoung Kang ,  Jeonggi Jin ,  Gilman Kang ,  Juil Choi ,  Dongchul Han

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/538

CPC classification number: H01L25/0657 ,  H01L23/3107 ,  H01L23/481 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/12105 ,  H01L2224/32146 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06555

Abstract: A semiconductor package includes a first redistribution structure, a first semiconductor chip on the first redistribution structure and including a first through-electrode, a second semiconductor chip on the first semiconductor chip and including a central portion vertically overlapping the first semiconductor chip and an outer portion horizontally offset from a sidewall of the first semiconductor chip, a molding layer in contact with the first redistribution structure, the first semiconductor chip, and the second semiconductor chip, a second redistribution structure on the second semiconductor chip and the molding layer, a first vertical connection wire extending through the molding layer and extending from the first redistribution structure to the second redistribution structure, and a second vertical connection wire extending through the molding layer and extending from the first redistribution structure to the outer portion of the second semiconductor chip.

公开(公告)号：US11935832B2

公开(公告)日：2024-03-19

申请号：US17938344

申请日：2022-10-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junyeong Heo ,  Unbyoung Kang ,  Donghoon Won

IPC: H01L23/528 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/76 ,  H01L21/768 ,  H01L21/78 ,  H01L23/00 ,  H01L23/48 ,  H01L23/485

CPC classification number: H01L23/5283 ,  H01L21/3065 ,  H01L21/78 ,  H01L23/481

Abstract: A semiconductor device includes a semiconductor substrate having a first surface and a second surface opposing each other, and a side surface between the first and second surfaces, and including a device region on the first surface a wiring structure on the surface of the semiconductor substrate, and having a dielectric layer and a metal wiring in the dielectric layer and electrically connected to the device region, and an insulating material layer on a side surface of the wiring structure and having a side surface connected to the side surface of the semiconductor substrate. The side surface of the insulating material layer has a first wave-shaped pattern in which concave-convex portions are repeated in a direction of the wiring structure that is perpendicular to the semiconductor substrate, and the side surface of the semiconductor substrate has a second wave-shaped pattern in which concave-convex portions are repeated in the direction.

公开(公告)号：US11688707B2

公开(公告)日：2023-06-27

申请号：US17307672

申请日：2021-05-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonho Jun ,  Sangsick Park ,  Unbyoung Kang

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L24/13 ,  H01L24/05 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05017 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05551 ,  H01L2224/05644 ,  H01L2224/13021 ,  H01L2224/16146 ,  H01L2224/16147 ,  H01L2224/16148 ,  H01L2225/06513

Abstract: Provided is a semiconductor package including: a first substrate having a first electrode pad and a first protective layer in which a cavity is formed; a first bump pad arranged in the cavity and connected to the first electrode pad; a second substrate facing the first substrate and having a second bump pad; and a bump structure in contact with the first bump pad and the second bump pad, wherein the first electrode pad has a trapezoidal shape, and the first bump pad has a flat upper surface and an inclined side surface extending along a side surface of the first electrode pad.

公开(公告)号：US20250079378A1

公开(公告)日：2025-03-06

申请号：US18949707

申请日：2024-11-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyoungjoo Lee ,  Unbyoung Kang ,  Sechul Park ,  Sangsick Park ,  Hyojin Yun ,  Teakhoon Lee ,  Juil Choi

IPC: H01L23/00 ,  H01L25/065

Abstract: A semiconductor package includes: a first semiconductor chip; a second semiconductor chip stacked on the first semiconductor chip; an underfill material layer interposed between the first semiconductor chip and the second semiconductor chip; and a first dam structure disposed on the first semiconductor chip. The first dam structure extends along an edge of the second semiconductor chip and includes unit dam structures apart from each other with a slit therebetween. A vertical level of an upper surface of the first dam structure is located between a vertical level of a lower surface of the second semiconductor chip and a vertical level of an upper surface of the second semiconductor chip. A first sidewall of the first dam structure is in contact with the underfill material layer and includes a flat surface parallel to a sidewall of the second semiconductor chip that faces the first sidewall of the first dam structure.