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81 条记录 (耗时 0.027 秒)

    Frequency comparator with hysteresis between locked and unlocked conditions
    21.
    发明授权
    Frequency comparator with hysteresis between locked and unlocked conditions 有权
    频率比较器在锁定和解锁条件之间具有滞后

    公开(公告)号：US06859107B1

    公开(公告)日：2005-02-22

    申请号：US10356695

    申请日：2003-01-30

    申请人： Yongsam Moon ,  Gijung Ahn ,  Deog-Kyoon Jeong

    发明人： Yongsam Moon ,  Gijung Ahn ,  Deog-Kyoon Jeong

    IPC分类号： H03L7/091 ,  H03L7/113 ,  H03L7/14 ,  H04L7/033 ,  H04L7/04 ,  H03L7/095

    CPC分类号： H04L7/033 ,  H03L7/091 ,  H03L7/113 ,  H03L7/14 ,  H04L7/04 ,  Y10S331/02

    摘要： A frequency comparator apparatus used with a reference clock, a voltage controlled oscillator circuit and a phase locked loop circuit includes a reference loop circuit wherein the reference loop circuit is activated when the frequency difference between the reference clock and the voltage controlled oscillator circuit is greater than about a first threshold. Also included is a data loop circuit wherein the data loop circuit is activated when the frequency difference between the reference clock and the voltage controlled oscillator circuit is less than about a second threshold.

    摘要翻译： 与参考时钟，压控振荡器电路和锁相环电路一起使用的频率比较器装置包括参考环路电路，其中当参考时钟和压控振荡器电路之间的频率差大于 约第一个门槛。 还包括数据环路电路，其中当参考时钟和压控振荡器电路之间的频率差小于约第二阈值时，数据环路电路被激活。

    CMOS low noise amplifier
    22.
    发明授权
    CMOS low noise amplifier 有权
    CMOS低噪声放大器

    公开(公告)号：US06754478B1

    公开(公告)日：2004-06-22

    申请号：US09709314

    申请日：2000-11-13

    申请人： Kyeongho Lee ,  Deog-Kyoon Jeong

    发明人： Kyeongho Lee ,  Deog-Kyoon Jeong

    IPC分类号： H04B106

    CPC分类号： H04B1/403 ,  H03F2200/372 ,  H03H2011/0494 ,  H03K9/00 ,  H03L7/0891 ,  H03L7/0995 ,  H03L7/1974 ,  H04B1/28 ,  H04B1/40

    摘要： A CMOS low noise amplifier (LNA) is provided that is formed without inductors. The CMOS LNA can be used for a single-chip CMOS RF receiver. The CMOS LNA can include a plurality of amplification stages coupled between an input terminal and an output terminal and a gain controller coupled to each of the plurality of amplifier stages, wherein the CMOS LNA does not include an inductor. Each of the amplification stages can have a symmetrically configured and sized first and second circuits to increase a dynamic range and a feedback loop.

    摘要翻译： 提供了一种无电感器形成的CMOS低噪声放大器（LNA）。 CMOS LNA可用于单芯片CMOS射频接收器。 CMOS LNA可以包括耦合在输入端子和输出端子之间的多个放大级和耦合到多个放大器级中的每一个的增益控制器，其中CMOS LNA不包括电感器。 每个放大级可以具有对称配置和尺寸的第一和第二电路以增加动态范围和反馈回路。

    System and method for high-speed, synchronized data communication
    23.
    发明授权
    System and method for high-speed, synchronized data communication 有权
    用于高速，同步数据通信的系统和方法

    公开(公告)号：US06587525B2

    公开(公告)日：2003-07-01

    申请号：US09814256

    申请日：2001-03-21

    申请人： Deog-Kyoon Jeong ,  Gijung Ahn

    发明人： Deog-Kyoon Jeong ,  Gijung Ahn

    IPC分类号： H04L700

    CPC分类号： H04L7/0334

    摘要： A system for transmission and recovery of original digital data includes an encoder, a transmitter, a receiver, a decoder, and an analog phase locked loop. The analog phase locked loop supplies a sender's clock to the transmitter and a receiver's clock to the receiver, where the sender's clock frequency is a first integer multiple of the system clock frequency, and the receiver's clock frequency is a second integer multiple of the sender's clock frequency within 0.1% tolerance. In a normal flow situation, data frames are output by the receiver in alternate cycles of the system clock. In an overflow situation, data frames are output by the receiver in consecutive cycles of the system clock. In an underflow situation, data frames are not output by the receiver in consecutive cycles of the system clock.

    摘要翻译： 用于传输和恢复原始数字数据的系统包括编码器，发射机，接收机，解码器和模拟锁相环。 模拟锁相环将发送器的时钟提供给发送器，并将接收器的时钟提供给接收器，其中发送器的时钟频率是系统时钟频率的第一个整数倍，接收器的时钟频率是发送器时钟的第二个整数倍 频率在0.1％以内。 在正常流量情况下，数据帧由系统时钟的交替周期由接收器输出。 在溢出情况下，数据帧由系统时钟的连续周期由接收器输出。 在下溢情况下，数据帧不会在系统时钟的连续周期内被接收机输出。

    Single chip CMOS transmitter/receiver
    24.
    发明授权
    Single chip CMOS transmitter/receiver 失效
    单芯片CMOS发射器/接收器

    公开(公告)号：US06335952B1

    公开(公告)日：2002-01-01

    申请号：US09121601

    申请日：1998-07-24

    申请人： Kyeongho Lee ,  Deog-Kyoon Jeong

    发明人： Kyeongho Lee ,  Deog-Kyoon Jeong

    IPC分类号： H03D318

    CPC分类号： H03H11/22 ,  H03D7/1441 ,  H03H2011/0494 ,  H03K9/00 ,  H03L7/0891 ,  H03L7/0995 ,  H03L7/1974 ,  H04B1/403

    摘要： A single chip RF communication system and method is provided including a transmitter and a receiver. The RF communication system in accordance with the present invention includes an antenna for receiving transmitting RF signals, a PLL for generating multi-phase clock signals having a frequency different from a carrier frequency in response to the multi-phase clock signals and a reference signal having the carrier frequency, a demodulation-mixing unit for mixing the received RF signals with the multi-phase clock signals having the frequency different from the carrier frequency to output the RF signals having a frequency reduced by the carrier frequency and an A/D converting unit for converting the RF signals from the mixing unit into digital signals.

    摘要翻译： 提供了包括发射机和接收机的单芯片RF通信系统和方法。 根据本发明的RF通信系统包括用于接收发射RF信号的天线，用于响应于多相时钟信号产生具有与载波频率不同的频率的多相时钟信号的PLL和具有 载波频率，用于将接收到的RF信号与具有与载波频率不同的频率的多相时钟信号混合的解调混合单元，以输出具有被载波频率减小的频率的RF信号和A / D转换单元 用于将来自混合单元的RF信号转换成数字信号。

    System and method for high-speed, synchronized data communication
    25.
    发明授权
    System and method for high-speed, synchronized data communication 有权

    公开(公告)号：US06229859B1

    公开(公告)日：2001-05-08

    申请号：US09146818

    申请日：1998-09-04

    申请人： Deog-Kyoon Jeong ,  Gijung Ahn

    发明人： Deog-Kyoon Jeong ,  Gijung Ahn

    IPC分类号： H04L700

    CPC分类号： H04L7/0334

    摘要： A system for transmission and recovery of original digital data includes an encoder, a transmitter, a receiver, a decoder, and an analog phase locked loop. The analog phase locked loop supplies a sender's clock to the transmitter and a receiver's clock to the receiver, where the sender's clock frequency is a first integer multiple of the system clock frequency, and the receiver's clock frequency is a second integer multiple of the sender's clock frequency within 0.1% tolerance. In a normal flow situation, data frames are output by the receiver in alternate cycles of the system clock. In an overflow situation, data frames are output by the receiver in consecutive cycles of the system clock. In an underflow situation, data frames are not output by the receiver in consecutive cycles of the system clock.

    VCO-mixer structure
    26.
    发明授权
    VCO-mixer structure 失效
    VCO混频器结构

    公开(公告)号：US06194947B1

    公开(公告)日：2001-02-27

    申请号：US09121863

    申请日：1998-07-24

    申请人： Kyeongho Lee ,  Deog-Kyoon Jeong

    发明人： Kyeongho Lee ,  Deog-Kyoon Jeong

    IPC分类号： G06F744

    CPC分类号： H04B1/28 ,  H03F2200/372 ,  H03H11/22 ,  H03H2011/0494 ,  H03K9/00 ,  H03L7/0891 ,  H03L7/0995 ,  H03L7/1974 ,  H04B1/40 ,  H04B1/403

    摘要： A VCO-mixer structure in accordance with the present invention includes a multi-phase VCO and a multi-phase mixer. The VCO includes a plurality of differential delay cells and the mixer includes a differential amplifying circuit and a combining circuit. The differential amplifying circuit of the multi-phase mixer includes two load resistors coupled to two differential amplifiers, respectively. The combining circuit includes bias transistors, first combining unit and second combining unit coupled to the bias transistors, respectively, and a current source coupled to the first and second combining units. The first combining unit includes a plurality of transistor units, and the second combining unit includes a second plurality of transistor units. Preferably, each of the plurality of transistor units includes a plurality of serially connected transistors, wherein the serially connected transistors are coupled in parallel with the serially connected transistors of the plurality of transistor units.

    摘要翻译： 根据本发明的VCO混频器结构包括多相VCO和多相混频器。 VCO包括多个差分延迟单元，并且混频器包括差分放大电路和组合电路。 多相混频器的差分放大电路分别包括耦合到两个差分放大器的两个负载电阻。 组合电路分别包括偏置晶体管，第一组合单元和耦合到偏置晶体管的第二组合单元，以及耦合到第一和第二组合单元的电流源。 第一组合单元包括多个晶体管单元，第二组合单元包括第二多个晶体管单元。 优选地，多个晶体管单元中的每一个包括多个串联连接的晶体管，其中串联连接的晶体管与多个晶体管单元的串联连接的晶体管并联耦合。

    Digital/analog converter
    30.
    发明授权
    Digital/analog converter 失效
    数字/模拟转换器

    公开(公告)号：US5621407A

    公开(公告)日：1997-04-15

    申请号：US370904

    申请日：1995-01-10

    申请人： Deog-Kyoon Jeong ,  Daejeong Kim

    发明人： Deog-Kyoon Jeong ,  Daejeong Kim

    IPC分类号： H03M1/66 ,  H03M3/02

    CPC分类号： H03M3/34 ,  H03M3/502

    摘要： A .DELTA..SIGMA. digital/analog converter comprising an interpolator for sampling an input digital signal at a desired ratio, a noise-shaping coder for quantizing an output signal from the interpolator into the coded bits and modulating a quantization error generated in the quantization, a differentiator for detecting an intersignal variation from an output signal from the noise-shaping coder, the intersignal variation indicating a difference between previous and present digital signal values, a digital logic unit for generating a desired control signal according to the intersignal variation detected by the differentiator, an internal digital/analog converter for performing charging and discharging operations in response to the desired control signal from the digital logic unit to output an analog signal corresponding to the input digital signal, and a filter for filtering an output signal from the internal digital/analog converter to remove a mixed noise therefrom. According to the present invention, a minimized number of passive devices is used to reduce an error amount resulting from a process deviation, miniaturize a chip and easily enhance the internal bits without expanding the chip size.

    摘要翻译： 一种DELTA SIGMA数字/模拟转换器，包括用于以期望比例对输入数字信号进行采样的内插器;噪声整形编码器，用于将来自内插器的输出信号量化为编码比特并调制在量化中产生的量化误差;微分器 用于检测来自噪声整形编码器的输出信号的信号间变化，指示前一个和当前数字信号值之间的差异的信号间变化;用于根据由微分器检测到的信号间变化产生期望控制信号的数字逻辑单元， 内部数字/模拟转换器，用于响应于来自数字逻辑单元的所需控制信号执行充电和放电操作，以输出对应于输入数字信号的模拟信号;以及滤波器，用于对来自内部数字/模拟 转换器以从其中去除混合噪声。 根据本发明，使用最小数量的无源器件来减少由于工艺偏差导致的误差量，使芯片小型化并且容易地增强内部位而不扩大芯片尺寸。