公开(公告)号：US06713386B1

公开(公告)日：2004-03-30

申请号：US10025304

申请日：2001-12-19

申请人： Rongxiang Hu ,  Yongbae Kim ,  Sang-Yun Lee ,  Hiroaki Takikawa ,  Shumay Dou ,  Sarah Neuman ,  Philippe Schoenborn ,  Keith Chao ,  Dilip Vijay ,  Kai Zhang ,  Masaichi Eda

发明人： Rongxiang Hu ,  Yongbae Kim ,  Sang-Yun Lee ,  Hiroaki Takikawa ,  Shumay Dou ,  Sarah Neuman ,  Philippe Schoenborn ,  Keith Chao ,  Dilip Vijay ,  Kai Zhang ,  Masaichi Eda

IPC分类号： H01L214763

CPC分类号： H01L21/76831 ,  H01L21/31144 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76826 ,  H01L21/76829

摘要： A method for forming a dual damascene interconnect in a dielectric layer is provided. Generally, a first aperture is etched in the dielectric. A poison barrier layer is formed over part of the dielectric, which prevents resist poisoning. A patterned mask is formed over the poison barrier layer. A second aperture is etched into the dielectric layer, wherein at least part of the first aperture shares the same area as at least part of the second aperture.

公开(公告)号：US06496399B1

公开(公告)日：2002-12-17

申请号：US09941372

申请日：2001-08-28

申请人： Jeong Yeol Choi ,  Sang-Yun Lee

发明人： Jeong Yeol Choi ,  Sang-Yun Lee

IPC分类号： G11C1500

CPC分类号： G11C15/04

摘要： A ternary CAM system includes a main memory cell configured to store complementary data signals D/D#. A first transistor has a source coupled to receive data signal D#, and a gate coupled to receive a compare signal C. A second transistor has a source coupled to receive data signal D, and a gate coupled to receive complementary compare signal C#. A third transistor has a gate coupled to drain regions of the first and second transistors. A mask cell storing a mask value is coupled to the source of the third transistor. A pre-charged match line is coupled to the drain of the third transistor. If compare signals C/C# match data signals D/D#, then the third transistor is turned off, thereby isolating match line and mask cell. If compare signals C/C# don't match data signals D/D#, then the third transistor is turned on, thereby coupling mask cell and match line.

摘要翻译： 三元CAM系统包括被配置为存储辅助数据信号D / D＃的主存储单元。 第一晶体管具有耦合以接收数据信号D＃的源极和耦合以接收比较信号C的栅极。第二晶体管具有耦合以接收数据信号D的源极和耦合以接收互补比较信号C＃的栅极。 第三晶体管具有耦合到第一和第二晶体管的漏极区的栅极。 存储掩模值的掩模单元耦合到第三晶体管的源极。 预充电匹配线耦合到第三晶体管的漏极。 如果比较信号C / C＃匹配数据信号D / D＃，则第三晶体管截止，从而隔离匹配线和掩模单元。 如果比较信号C / C＃不匹配数据信号D / D＃，则第三晶体管导通，从而耦合屏蔽单元和匹配线。

公开(公告)号：US20240021689A1

公开(公告)日：2024-01-18

申请号：US18233293

申请日：2023-08-11

申请人： Sang-Yun Lee

发明人： Sang-Yun Lee

IPC分类号： H01L29/423 ,  H01L29/78 ,  H01L25/18 ,  H01L29/40 ,  H01L29/66 ,  H01L29/792 ,  H01L29/06 ,  H10B12/00 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC分类号： H01L29/4234 ,  H01L29/7827 ,  H01L25/18 ,  H01L29/401 ,  H01L29/66833 ,  H01L29/7926 ,  H01L29/66666 ,  H01L29/0649 ,  H10B12/05 ,  H10B12/31 ,  H10B12/50 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

摘要： Structures and methods that facilitate the formation of gate contacts for vertical transistors constructed with semiconductor pillars and spacer-like gates are disclosed. In a first embodiment, a gate contact rests on an extended gate region, a piece of a gate film, patterned at a side of a vertical transistor at the bottom of the gate. In a second embodiment, an extended gate region is patterned on top of one or more vertical transistors, resulting in a modified transistor structure. In a third embodiment, a gate contact rests on a top surface of a gate merged between two closely spaced vertical transistors. Optional methods and the resultant intermediate structures are included in the first two embodiments in order to overcome the related topography and ease the photolithography. The third embodiment includes alternatives for isolating the gate contact from the semiconductor pillars or for isolating the affected semiconductor pillars from the substrate.

公开(公告)号：US11424248B2

公开(公告)日：2022-08-23

申请号：US17032944

申请日：2020-09-25

申请人： Sang-Yun Lee

发明人： Sang-Yun Lee

IPC分类号： H01L27/108 ,  H01L29/66 ,  H01L29/78

摘要： The invention involves a method of manufacturing a bonded semiconductor structure, comprising providing a support substrate which carries a transistor, and providing an interconnect region earned by the support substrate. The interconnect region includes a first multiple bypass bitline having an upper bypass interconnect and upper bypass via. The method includes providing a first conductive bonding layer carried by the interconnect region, wherein the first conductive bonding layer is connected to the upper bypass interconnect through the upper bypass via, and providing a vertical transistor carried by the first conductive bonding layer, the vertical transistor being in communication with the transistor through the interconnect region. The first multiple bypass bitline reduces the impedance experienced by the vertical transistor.

公开(公告)号：US20220189515A1

公开(公告)日：2022-06-16

申请号：US17122173

申请日：2020-12-15

申请人： Sang-Yun Lee

发明人： Sang-Yun Lee

IPC分类号： G11C7/06 ,  G11C7/12 ,  G11C8/10 ,  H01L23/528 ,  H01L27/092 ,  H01L29/786

摘要： Structures for 3D sense amplifiers for 3D memories are disclosed. A first embodiment uses one type of vertical transistors in constructing 3D sense amplifiers. A second embodiment uses both n- and p-type transistors for 3D sense amplifiers. Either or both of n- and p-type transistors are vertical transistors. The n- and p-type transistors may reside on different levels, or on the same level above a substrate if both are vertical transistors. In any embodiment, different options are available for gate contact formation. In any embodiments and options or alternatives thereof, one or more sense-enable circuits may be used. Sense amplifiers for several bit lines may be staggered on one or both sides of a memory array. Column multiplexers may be used to couple particular bit lines to data outputs. Bit-line multiplexers may be used to couple certain bit lines to shared 3D sense amplifiers.

公开(公告)号：US09328407B2

公开(公告)日：2016-05-03

申请号：US13900751

申请日：2013-05-23

申请人： Sang-Yun Lee ,  Sung-Woo Jung

发明人： Sang-Yun Lee ,  Sung-Woo Jung

IPC分类号： B05C17/08 ,  C23C14/04 ,  B05C21/00 ,  C23C14/12 ,  H01L51/00

CPC分类号： C23C14/042 ,  B05C17/08 ,  B05C21/005 ,  C23C14/12 ,  H01L51/0011

摘要： A clamp configured to clamp an end of a unit mask supported while a tensile force is applied to the unit mask includes a clamp main body, and a rotation contact portion rotatably supported by the clamp main body and directly contacting the end of the unit mask.

摘要翻译： 夹持构造成将张力施加到单位掩模上的单元掩模的端部夹持的夹具包括夹具主体和由夹具主体可旋转地支撑并直接接触单元掩模的端部的旋转接触部。

公开(公告)号：US08828619B2

公开(公告)日：2014-09-09

申请号：US12863594

申请日：2008-02-13

申请人： Young-Moo Lee ,  Chang-Hyun Lee ,  Sang-Yun Lee

发明人： Young-Moo Lee ,  Chang-Hyun Lee ,  Sang-Yun Lee

IPC分类号： H01M8/10

CPC分类号： H01M8/1088 ,  H01M8/1025 ,  H01M8/1027 ,  H01M8/103 ,  H01M8/1032 ,  H01M8/1034 ,  H01M8/1039 ,  H01M8/1048 ,  H01M8/1051 ,  H01M2008/1095 ,  Y02P70/56

摘要： A proton exchange polymer membrane whose surface is treated by direct fluorination using a fluorine gas, a membrane-electrode assembly, and a fuel cell comprising the same are provided. The proton exchange polymer membrane of the present invention exhibits improved proton conductivity, high dimensional stability, and decreased methanol permeability through introducing hydrophobic fluorine having high electronegativity to the surface of the polymer membrane. Therefore, the proton exchange polymer membrane with excellent electrochemical properties of the present invention can be preferably utilized as polymer electrolyte membrane for fuel cell, generating electric energy from chemical energy of fuels.

摘要翻译： 提供了通过使用氟气直接氟化处理其表面的质子交换聚合物膜，膜电极组件和包含该质子交换聚合物膜的燃料电池。 本发明的质子交换聚合物膜通过将具有高电负性的疏水性氟引入聚合物膜的表面，显示出改进的质子传导性，高尺寸稳定性和降低的甲醇渗透性。 因此，本发明的具有优异的电化学特性的质子交换聚合物膜可以优选用作燃料电池的聚合物电解质膜，从燃料的化学能产生电能。

公开(公告)号：US08723335B2

公开(公告)日：2014-05-13

申请号：US12847244

申请日：2010-07-30

申请人： Sang-Yun Lee

发明人： Sang-Yun Lee

IPC分类号： H01L29/40

CPC分类号： H01L21/823871 ,  H01L21/187 ,  H01L23/481 ,  H01L24/24 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L2224/24145 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2224/83138 ,  H01L2224/83192 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2924/12036 ,  H01L2924/1301 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00

摘要： A semiconductor structure includes an interconnect region, and a material transfer region coupled to the interconnect region through a bonding interface. The semiconductor structure includes a capping layer sidewall portion which extends annularly around the material transfer region and covers the bonding interface. The capping layer sidewall portion restricts the flow of debris from the bonding interface.

摘要翻译： 半导体结构包括互连区域和通过接合界面耦合到互连区域的材料转移区域。 半导体结构包括覆盖层侧壁部分，其围绕材料传输区域环形地延伸并且覆盖接合界面。 封盖层侧壁部分限制粘结界面上的碎屑流。

公开(公告)号：US08477016B2

公开(公告)日：2013-07-02

申请号：US11574189

申请日：2006-09-08

申请人： Kyung-Ho Seo ,  Won-Jun Lee ,  Ji-Hoon Myung ,  Jin-Hee Yoon ,  Joo-Mun Lee ,  Sang-Yun Lee ,  Myung-Sung Lee

发明人： Kyung-Ho Seo ,  Won-Jun Lee ,  Ji-Hoon Myung ,  Jin-Hee Yoon ,  Joo-Mun Lee ,  Sang-Yun Lee ,  Myung-Sung Lee

IPC分类号： H04Q5/22

CPC分类号： G06K7/0008 ,  G06K7/10049

摘要： The RFID system includes an RFID reader for sending information selected from among collision type information, idle type information, and readable type information, to all of the RFID tags depending on the number of signals in the corresponding time slot, and RFID tags for performing functions, in which, when information, indicating that a current time slot is a collision type, is fed back from the RFID reader, each of RFID tags selects one arbitrary value of either 0 or 1 and is assigned a time slot, in which a corresponding RFID tag will send a signal to the RFID reader, based on the selected value, a single tag group that caused a collision is divided into two sub-groups depending on the assigned time slots, and tags of the sub-groups send signals, including IDs thereof, to the RFID reader in different time slots for the respective sub-groups.

摘要翻译： RFID系统包括RFID读取器，用于根据相应时隙中的信号数量将从冲突类型信息，空闲类型信息和可读类型信息中选出的信息发送到所有RFID标签，以及用于执行功能的RFID标签 其中，当从RFID读取器反馈指示当前时隙是冲突类型的信息时，每个RFID标签选择0或1中的任意值，并且分配一个时隙，其中相应的 RFID标签将根据所选值向RFID读取器发送信号，根据所分配的时隙将导致冲突的单个标签组划分为两个子组，并且子组的标签发送信号，包括 其ID对于相应子组的不同时隙中的RFID读取器。

公开(公告)号：US20120003815A1

公开(公告)日：2012-01-05

申请号：US13175293

申请日：2011-07-01

申请人： Sang-Yun Lee

发明人： Sang-Yun Lee

IPC分类号： H01L21/304

CPC分类号： H01L21/304 ,  H01L21/268 ,  H01L21/76254 ,  H01L21/76259

摘要： A method of fabricating a semiconductor substrate includes providing a first semiconductor substrate, which includes a detaching layer spaced from an upper surface of the first semiconductor substrate; forming an ion-implanted layer proximate to an edge of the detaching layer; bonding a second semiconductor substrate to the first semiconductor substrate; forming a crack in the ion-implanted layer in response to applying stress to the ion-implanted layer; and detaching a portion of the first semiconductor substrate in response to cleaving through the crack.

摘要翻译： 一种制造半导体衬底的方法包括提供第一半导体衬底，其包括与第一半导体衬底的上表面间隔开的分离层; 在所述分离层的边缘附近形成离子注入层; 将第二半导体衬底接合到所述第一半导体衬底; 响应于向离子注入层施加应力而在离子注入层中形成裂纹; 以及响应于通过所述裂纹的裂开而分离所述第一半导体衬底的一部分。