公开(公告)号：US5998974A

公开(公告)日：1999-12-07

申请号：US196701

申请日：1998-11-20

申请人： Minoru Sudo ,  Takayuki Takashina ,  Yoshikazu Kojima ,  Sadashi Shimoda ,  Hiroshi Mukainakano

发明人： Minoru Sudo ,  Takayuki Takashina ,  Yoshikazu Kojima ,  Sadashi Shimoda ,  Hiroshi Mukainakano

IPC分类号： G01R31/36 ,  H01M10/44 ,  H02H7/18 ,  H02J7/00 ,  H02J7/02 ,  H02J7/10 ,  H02J7/14 ,  H01M10/46

CPC分类号： H02J7/1438 ,  H02J7/0011 ,  H02J7/0018 ,  H02J7/0026 ,  H02J7/0031 ,  H02J7/0034 ,  H02J7/0063 ,  H02J7/008 ,  H02J7/0086 ,  H02J2007/004

摘要： A charge/discharge control circuit has a voltage detector for detecting a voltage level of a secondary cell, a switch connected in series with the secondary cell, and a control circuit connected in parallel with the voltage detector for receiving and processing an output signal of the voltage detector and controlling an impedance of the switch. The voltage detector, the switch and the control circuit are integrated in a single substrate. In a preferred embodiment, the switch comprises an external connection terminal and a second terminal connected to the secondary cell, a first IGFET connected between the first and second terminals, a second IGFET connectected between the first terminal and a substrate electrode of the first IGFET, and a third IGFET connected between the second terminal and the substrate electrode of the first IGFET.

摘要翻译： 充放电控制电路具有用于检测二次电池的电压电平的电压检测器，与二次电池串联连接的开关，以及与电压检测器并联连接的控制电路，用于接收和处理二次电池的输出信号 电压检测器并控制开关的阻抗。 电压检测器，开关和控制电路集成在单个基板中。 在优选实施例中，开关包括外部连接端子和连接到二次电池的第二端子，连接在第一和第二端子之间的第一IGFET，在第一端子和第一IGFET的基板电极之间连接的第二IGFET， 以及连接在第一IGFET的第二端子和衬底电极之间的第三IGFET。

公开(公告)号：US5982461A

公开(公告)日：1999-11-09

申请号：US834288

申请日：1992-02-14

申请人： Yutaka Hayashi ,  Masaaki Kamiya ,  Yoshikazu Kojima ,  Hiroaki Takasu

发明人： Yutaka Hayashi ,  Masaaki Kamiya ,  Yoshikazu Kojima ,  Hiroaki Takasu

IPC分类号： G02F1/136 ,  G02F1/1362 ,  G02F1/1368 ,  G09F9/30 ,  G09G3/20 ,  G09G3/36 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786

CPC分类号： G02F1/13454 ,  G02F1/1362 ,  G02F2202/105

摘要： A light valve device has a drive substrate integrated with a drive electrode. A transistor is connected to the drive electrode and a driving circuit energizes the drive electrode through the transistor. An opposed substrate is provided opposed to the drive electrode, and an electrooptical material layer is disposed between the drive substrate and the opposed substrate. The drive substrate has a structure comprising a substrate layer and a semiconductor single crystal thin film layer. The semiconductor single crystal thin film layer is made by thinning a semiconductor single crystal wafer which has been bonded to the substrate layer. The light valve device has a small size and high pixel density and can be formed using miniaturization technology. The light valve can be used for a small size, high resolution video projector and a color matrix display device.

摘要翻译： PCT No.PCT / JP91 / 00580 Sec。 371日期：1992年2月14日 102（e）日期1992年2月14日PCT 1991年4月26日PCT PCT。 WO91 / 17471 PCT出版物 日期1991年11月14日光阀装置具有与驱动电极集成的驱动基板。 晶体管连接到驱动电极，驱动电路通过晶体管对驱动电极通电。 相对的基板与驱动电极相对设置，电光材料层设置在驱动基板和相对的基板之间。 驱动基板具有包括基板层和半导体单晶薄膜层的结构。 半导体单晶薄膜层通过使已结合到基底层的半导体单晶晶片变薄来制造。 光阀装置具有小尺寸和高像素密度，并且可以使用小型化技术形成。 光阀可用于小尺寸，高分辨率的视频投影机和彩色矩阵显示设备。

公开(公告)号：US5950085A

公开(公告)日：1999-09-07

申请号：US620929

申请日：1996-03-22

申请人： Yoshikazu Kojima ,  Tetsuya Maeda

发明人： Yoshikazu Kojima ,  Tetsuya Maeda

IPC分类号： H01L21/8247 ,  H01L21/336 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/66825 ,  H01L29/42324 ,  H01L29/7883

摘要： A method of manufacturing an electrically erasable semiconductor non-volatile memory device comprises forming a field insulating film on a surface of a semiconductor substrate having a first conductivity type. A gate insulating film is formed on the surface of the semiconductor substrate. Source and drain regions having a second conductivity type are formed in the surface of the semiconductor substrate in spaced-apart relationship with each other by introducing impurity ions having the second conductivity type into the semiconductor substrate with an acceleration energy sufficient to form a peak value of impurity concentration at a depth of more than approximately 500 .ANG. from the surface of the semiconductor substrate. The gate insulating film is then etched on the drain region to form a tunnel region having opposite sides connected to the field insulating film. Thereafter, a tunnel insulating film is formed on the tunnel region and a floating gate electrode is formed over the source region, the drain region and the semiconductor substrate through the gate insulating film and the tunnel insulating film. A control insulating film is then formed on the floating gate electrode, and a control gate electrode is formed over the floating gate electrode through the control insulating film.

摘要翻译： 一种制造电可擦除半导体非易失性存储器件的方法包括在具有第一导电类型的半导体衬底的表面上形成场绝缘膜。 在半导体衬底的表面上形成栅极绝缘膜。 具有第二导电类型的源极和漏极区域以相互间隔的关系形成在半导体衬底的表面中，通过将具有第二导电类型的杂质离子引入到半导体衬底中，具有足以形成峰值的加速度能量 在半导体衬底的表面上的深度大于约500的杂质浓度。 然后在漏极区上蚀刻栅极绝缘膜，以形成具有连接到场绝缘膜的相对侧的隧道区域。 此后，在隧道区域上形成隧道绝缘膜，并且通过栅极绝缘膜和隧道绝缘膜在源区域，漏极区域和半导体衬底上形成浮栅电极。 然后在浮栅上形成控制绝缘膜，通过控制绝缘膜在浮栅上形成控制栅电极。

公开(公告)号：US5834809A

公开(公告)日：1998-11-10

申请号：US568537

申请日：1995-12-07

申请人： Yuichi Kato ,  Yoshikazu Kojima

发明人： Yuichi Kato ,  Yoshikazu Kojima

IPC分类号： H01L21/265 ,  H01L21/316 ,  H01L21/8238 ,  H01L23/52 ,  H01L27/092 ,  H01L27/12 ,  H01L29/10 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L29/1087 ,  H01L21/823878 ,  H01L27/092

摘要： A MIS transistor comprises a semiconductor substrate having a first conductivity type, a source region and a drain region disposed in the semiconductor substrate in spaced-apart relation from one another and having a second conductivity type, and an insulating film disposed on the surface of the semiconductor substrate. A gate electrode is disposed on the insulating film between the source region and the drain region. A diffused region having the first conductivity type is disposed in the semiconductor substrate and in contact with the source region. An oxide film is disposed on the diffused region.

摘要翻译： MIS晶体管包括具有第一导电类型，源极区域和漏极区域的半导体衬底，所述第一导电类型，源极区域和漏极区域彼此间隔开地设置在半导体衬底中并且具有第二导电类型，以及设置在所述半导体衬底的表面上的绝缘膜 半导体衬底。 在源极区域和漏极区域之间的绝缘膜上设置栅电极。 具有第一导电类型的扩散区域设置在半导体衬底中并与源极区域接触。 氧化膜设置在扩散区域上。

公开(公告)号：US5663589A

公开(公告)日：1997-09-02

申请号：US314140

申请日：1994-09-28

申请人： Yutaka Saitoh ,  Jun Osanai ,  Yoshikazu Kojima ,  Kazutoshi Ishii

发明人： Yutaka Saitoh ,  Jun Osanai ,  Yoshikazu Kojima ,  Kazutoshi Ishii

IPC分类号： H01L21/8234 ,  H01L27/08 ,  H01L27/088 ,  H01L29/76 ,  H01L21/04

CPC分类号： H01L27/0814 ,  Y10S257/907 ,  Y10S257/91

摘要： A semiconductor integrated device having a current regulating diode may be substantially reduced in size and improved in performance by forming the current regulating diode of a plurality of MOS transistors each having a gate, a drain region, and a source region formed in a semiconductor substrate, the source regions and the substrate regions being electrically coupled to each other, the drain regions of at least two of the MOS transistors being electrically coupled, and the source regions of each of the MOS transistors being electrically coupled, the coupled drain regions, the coupled source regions, and the coupled gates forming a drain terminal, a source terminal and a gate terminal, respectively. In order to set a desired regulated current, selected coupling lines in the current regulating diode may be cut. This may be accomplished, for example, by measuring a first current which flows in the drain terminal while applying a first voltage to the gate terminal and a second voltage to the drain terminal relative to an electric potential of the source terminal, then measuring a second current which flows in the drain terminal while applying a third voltage to the gate terminal and the second voltage to the drain terminal relative to an electric potential of the source terminal. In order to achieve the desired current characteristic, selected conductive lines between coupled drains or between coupled sources are then cut.

摘要翻译： 具有电流调节二极管的半导体集成器件可以通过形成多个MOS晶体管的电流调节二极管来大大减小尺寸并提高其性能，每个MOS晶体管具有形成在半导体衬底中的栅极，漏极区域和源极区域， 源极区域和衬底区域彼此电耦合，至少两个MOS晶体管的漏极区域电耦合，并且每个MOS晶体管的源极区域电耦合，耦合的漏极区域，耦合的 源极区域和耦合栅极分别形成漏极端子，源极端子和栅极端子。 为了设定期望的调节电流，可以切断电流调节二极管中的选择的耦合线。 这可以例如通过测量在漏极端子中流动的第一电流，同时向栅极端子施加第一电压，并且相对于源极端子的电位向漏极端子施加第二电压，然后测量第二电压 相对于源极端子的电位向漏极端子施加第三电压而向漏极端子施加第三电压而流过漏极端子的电流。 为了实现期望的电流特性，然后切割耦合的漏极之间或耦合的源之间的选定的导线。

公开(公告)号：US5449637A

公开(公告)日：1995-09-12

申请号：US128059

申请日：1993-09-27

申请人： Yutaka Saito ,  Yoshikazu Kojima ,  Kazutoshi Ishii

发明人： Yutaka Saito ,  Yoshikazu Kojima ,  Kazutoshi Ishii

IPC分类号： H01L21/265 ,  H01L21/266 ,  H01L21/8238 ,  H01L27/092

CPC分类号： H01L21/8238

摘要： An electroconductive or insulative film 100 is formed over a surface of a semiconductor substrate 1. A first photoresist 101 is coated over the film 100, and is then patterned. The film 100 is selectively removed by etching to expose a given area of the substrate 1. Subsequently an impurity of the first conductivity type is doped into the exposed area to form a first impurity region. After removing the first photoresist 101, a second photoresist 103 is coated entirely over the film 100, and is then patterned. Subsequently, the film 100 is selectively removed from another given area by etching. Another impurity of the second conductivity type is doped into the exposed area to form a second impurity region 104. Only the two steps of the photoresist patterning are carried out to form the impurity regions of the different conductivity types, thereby reducing production cost of the semiconductor device. The impurity can be doped by ion implantation while covering the film 100 with the photoresist, thereby facilitating micronization and integration of the semiconductor device.

摘要翻译： 在半导体衬底1的表面上形成导电或绝缘膜100.第一光致抗蚀剂101涂覆在膜100上，然后被图案化。 通过蚀刻选择性地去除膜100以暴露衬底1的给定区域。随后将第一导电类型的杂质掺杂到暴露区域中以形成第一杂质区域。 在去除第一光致抗蚀剂101之后，将第二光致抗蚀剂103整个涂覆在膜100上，然后被图案化。 随后，通过蚀刻从另一给定区域选择性地去除膜100。 第二导电类型的另一杂质被掺杂到暴露区域中以形成第二杂质区域104.只进行光致抗蚀剂图案化的两个步骤以形成不同导电类型的杂质区域，从而降低半导体的制造成本 设备。 可以通过离子注入来掺杂杂质，同时用光致抗蚀剂覆盖膜100，从而有助于半导体器件的微粉化和集成。

公开(公告)号：USD339513S

公开(公告)日：1993-09-21

申请号：US306036

申请日：1989-02-01

申请人： Yoshikazu Kojima

设计人： Yoshikazu Kojima

公开(公告)号：US4996995A

公开(公告)日：1991-03-05

申请号：US310736

申请日：1989-02-14

申请人： Yoshikazu Kojima

发明人： Yoshikazu Kojima

IPC分类号： F21V33/00 ,  A24F19/00 ,  A24F19/10

CPC分类号： A24F19/0042

摘要： An ashtray which has a main body including a tray for receiving ashes and a housing having an opening facing upwardly for housing the tray therein, a lid member for covering the opening of the housing therewith, a hinge assembly for rotatably connecting the lid member to the main body, an air cleaning means disposed at the lid member for removing impurities from the air, the air cleaning means including a fan for exhausting the air, a drive means for driving the fan and an air cleaner for removing impurities from the air and a light means for lighting the main body and the lid member. The ashtray can be used in a dimly-lit-place as well as in a well-lit place, and is able to clean the air by removing impurities, including smoke emitted from cigarettes or other smoking materials.

摘要翻译： 一种烟灰缸，其主体包括用于接收灰分的托盘和具有面向上的开口的壳体，用于容纳托盘;盖构件，用于覆盖壳体的开口;铰链组件，用于将盖构件可旋转地连接到 主体，设置在盖构件上用于从空气中除去杂质的空气净化装置，空气净化装置包括用于排出空气的风扇，用于驱动风扇的驱动装置和用于从空气中除去杂质的空气净化器 用于照亮主体和盖构件的光装置。 烟灰缸可以在昏暗的地方以及光线充足的地方使用，并且可以通过除去杂质（包括从香烟或其他吸烟材料排出的烟雾）来清洁空气。

公开(公告)号：US4639755A

公开(公告)日：1987-01-27

申请号：US413492

申请日：1982-08-31

申请人： Masayuki Namiki ,  Masaaki Kamiya ,  Yoshikazu Kojima ,  Kojiro Tanaka

发明人： Masayuki Namiki ,  Masaaki Kamiya ,  Yoshikazu Kojima ,  Kojiro Tanaka

IPC分类号： H01L29/73 ,  G01K7/01 ,  H01L21/331 ,  H01L27/02 ,  H01L27/082 ,  H01L27/092 ,  H01L27/16 ,  H01L29/66 ,  H01L35/00 ,  H01L23/56

CPC分类号： H01L27/16 ,  H01L27/0211 ,  H01L27/0825 ,  H01L27/092 ,  H01L29/66

摘要： A thermosensitive semiconductor device has a semiconductor substrate of one conductivity type which is used as the common collector of at least two Darlington-connected transistors. The base of the first stage transistor is connected to the common collector to form a first terminal and the emitter of the final stage transistor forms a second terminal. A constant current source is connected between the first and second terminals. To reduce deviations in the temperature response, a second collector region can be used and which can extend to a depth deeper than the depth of the emitter of the final stage transistor to absorb some of the carriers injected by the emitter.

摘要翻译： 热敏半导体器件具有一种导电类型的半导体衬底，其用作至少两个达林顿连接的晶体管的公共集电极。 第一级晶体管的基极连接到公共集电极以形成第一端子，并且最后级晶体管的发射极形成第二端子。 恒流源连接在第一和第二端子之间。 为了减少温度响应的偏差，可以使用第二集电极区域，并且其可以延伸到比最终级晶体管的发射极的深度更深的深度，以吸收由发射极注入的一些载流子。

公开(公告)号：US06306709B1

公开(公告)日：2001-10-23

申请号：US09270648

申请日：1999-03-16

申请人： Masanori Miyagi ,  Haruo Konishi ,  Kazuaki Kubo ,  Yoshikazu Kojima ,  Toru Shimizu ,  Yutaka Saitoh ,  Toru Machida ,  Tetsuya Kaneko

发明人： Masanori Miyagi ,  Haruo Konishi ,  Kazuaki Kubo ,  Yoshikazu Kojima ,  Toru Shimizu ,  Yutaka Saitoh ,  Toru Machida ,  Tetsuya Kaneko

IPC分类号： H01L21336

CPC分类号： H01L29/78696 ,  H01L21/3226 ,  H01L21/823462 ,  H01L27/0705 ,  H01L29/1041 ,  H01L29/1045 ,  H01L29/66757

摘要： In a MISFET, areas where a channel surface of a channel region is inverted by a first gate voltage and areas where the channel surface is inverted by a second gate voltage are provided in the channel region of the MISFET in plane as components thereof. The channel region 104 having a first impurity concentration determined by a surface concentration of a P-type semiconductor substrate and a channel region 105 having a second impurity concentration determined by doping an impurity to the region selected by a pattern 106 of a mask for doping impurity by ion implantation and others are provided in a channel region of an N-type MOSFET on the P-type semiconductor substrate. The channel region 104 having the first impurity concentration and the channel region 105 having the second impurity concentration are divided into a plurality of plane shapes. The channel region of the same MOSFET may be structured by the plurality of plane shapes having the plurality of impurity concentrations as described above and a threshold voltage of the MOSFET may be readily set to a desired value in response to a plane area ratio of the area having the first impurity concentration and the area having the second impurity concentration, allowing to realize a high performance semiconductor integrated circuit device at low cost.

摘要翻译： 在MISFET中，在MISFET的沟道区域中设置沟道区域的沟道表面被第一栅极电压反转的区域和沟道表面由第二栅极电压反转的区域，作为其组成。 具有由P型半导体衬底的表面浓度确定的第一杂质浓度的通道区域104和通过掺杂杂质确定的第二杂质浓度的沟道区域105，所述沟道区域105由用于掺杂杂质的掩模的图案106选择的区域 通过离子注入等设置在P型半导体衬底上的N型MOSFET的沟道区中。 具有第一杂质浓度的沟道区域104和具有第二杂质浓度的沟道区域105被分成多个平面形状。 相同MOSFET的沟道区域可以由具有如上所述的多个杂质浓度的多个平面形状构成，并且可以根据区域的平面面积比容易地将MOSFET的阈值电压设置为期望值 具有第一杂质浓度和具有第二杂质浓度的面积，从而以低成本实现高性能半导体集成电路器件。