公开(公告)号：US20160225772A1

公开(公告)日：2016-08-04

申请号：US15007259

申请日：2016-01-27

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Masashi TSUBUKU ,  Kazuaki OHSHIMA ,  Masashi FUJITA ,  Daigo SHIMADA ,  Tsutomu MURAKAWA

IPC: H01L27/105 ,  H01L29/786 ,  H01L27/12

CPC classification number: H01L29/7869 ,  G11C11/401 ,  H01L27/1156 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/78618 ,  H01L29/78621 ,  H01L29/78648 ,  H01L29/78696

Abstract: A semiconductor device that can measure a minute current. The semiconductor device includes a first transistor, a second transistor, a node, and a capacitor. The first transistor includes an oxide semiconductor in a channel formation region. The node is electrically connected to a gate of the second transistor and a first terminal of the capacitor. The node is brought into an electrically floating state by turning off the first transistor after a potential V0 is supplied. Change in a potential VFN of the node over time is expressed by Formula (1). In Formula (1), t is elapsed time after the node is brought into the electrically floating state, τ is a constant with a unit of time, and β is a constant greater than or equal to 0.4 and less than or equal to 0.6. V FN  ( t ) = V 0 ×  - ( t τ ) β ( 1 )

Abstract translation: 可以测量微小电流的半导体器件。 半导体器件包括第一晶体管，第二晶体管，节点和电容器。 第一晶体管包括沟道形成区中的氧化物半导体。 该节点电连接到第二晶体管的栅极和电容器的第一端子。 通过在提供电位V0之后关闭第一晶体管，使节点进入电浮动状态。 随着时间的推移，节点的潜在VFN的变化由公式（1）表示。 在公式（1）中，t是节点进入电浮动状态之后的经过时间，τ是以时间为单位的常数，β是大于或等于0.4且小于等于0.6的常数。 V FN（t）= V 0× - （tτ）β（1）

公开(公告)号：US20160056299A1

公开(公告)日：2016-02-25

申请号：US14931224

申请日：2015-11-03

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tatsuya HONDA ,  Masashi TSUBUKU ,  Yusuke NONAKA ,  Takashi SHIMAZU ,  Shunpei YAMAZAKI

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/417

CPC classification number: H01L29/78693 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/7869

Abstract: A decrease in on-state current in a semiconductor device including an oxide semiconductor film is suppressed. A transistor including an oxide semiconductor film, an insulating film which includes oxygen and silicon, a gate electrode adjacent to the oxide semiconductor film, the oxide semiconductor film provided to be in contact with the insulating film and overlap with at least the gate electrode, and a source electrode and a drain electrode electrically connected to the oxide semiconductor film. In the oxide semiconductor film, a first region which is provided to be in contact with the interface with the insulating film and have a thickness less than or equal to 5 nm has a silicon concentration lower than or equal to 1.0 at. %, and a region in the oxide semiconductor film other than the first region has lower silicon concentration than the first region.

公开(公告)号：US20150349133A1

公开(公告)日：2015-12-03

申请号：US14813408

申请日：2015-07-30

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Masashi TSUBUKU ,  Ryosuke WATANABE ,  Masashi OOTA ,  Noritaka ISHIHARA ,  Koki INOUE

IPC: H01L29/786

CPC classification number: H01L29/1054 ,  H01L22/14 ,  H01L29/247 ,  H01L29/42356 ,  H01L29/42384 ,  H01L29/78606 ,  H01L29/7869 ,  H01L29/78693 ,  H01L29/78696 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An oxide semiconductor stacked film which does not easily cause a variation in electrical characteristics of a transistor and has high stability is provided. Further, a transistor which includes the oxide semiconductor stacked film in its channel formation region and has stable electrical characteristics is provided. An oxide semiconductor stacked film includes a first oxide semiconductor layer, a second oxide semiconductor layer, and a third oxide semiconductor layer which are sequentially stacked and each of which contains indium, gallium, and zinc. The content percentage of indium in the second oxide semiconductor layer is higher than that in the first oxide semiconductor layer and the third oxide semiconductor layer, and the absorption coefficient of the oxide semiconductor stacked film, which is measured by the CPM, is lower than or equal to 3×10−3/cm in an energy range of 1.5 eV to 2.3 eV.

公开(公告)号：US20150303072A1

公开(公告)日：2015-10-22

申请号：US14790668

申请日：2015-07-02

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Junichiro SAKATA ,  Masashi TSUBUKU ,  Kengo AKIMOTO ,  Miyuki HOSOBA ,  Masayuki SAKAKURA ,  Yoshiaki OIKAWA

IPC: H01L21/477 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L21/477 ,  G02F1/133345 ,  G02F1/1368 ,  H01L21/02565 ,  H01L21/02664 ,  H01L27/1225 ,  H01L27/1248 ,  H01L27/1251 ,  H01L27/1259 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78696

Abstract: An object is to provide a display device with excellent display characteristics, where a pixel circuit and a driver circuit provided over one substrate are formed using transistors which have different structures corresponding to characteristics of the respective circuits. The driver circuit portion includes a driver circuit transistor in which a gate electrode layer, a source electrode layer, and a drain electrode layer are formed using a metal film, and a channel layer is formed using an oxide semiconductor. The pixel portion includes a pixel transistor in which a gate electrode layer, a source electrode layer, and a drain electrode layer are formed using an oxide conductor, and a semiconductor layer is formed using an oxide semiconductor. The pixel transistor is formed using a light-transmitting material, and thus, a display device with higher aperture ratio can be manufactured.

Abstract translation: 本发明的目的是提供具有优异显示特性的显示装置，其中使用具有对应于各个电路的特性的不同结构的晶体管形成设置在一个基板上的像素电路和驱动电路。 驱动器电路部分包括驱动电路晶体管，其中使用金属膜形成栅电极层，源电极层和漏电极层，并且使用氧化物半导体形成沟道层。 像素部分包括其中使用氧化物导体形成栅电极层，源电极层和漏电极层的像素晶体管，并且使用氧化物半导体形成半导体层。 像素晶体管使用透光材料形成，因此可以制造具有较高开口率的显示装置。

公开(公告)号：US20150241510A1

公开(公告)日：2015-08-27

申请号：US14625984

申请日：2015-02-19

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Masashi TSUBUKU ,  Kazuma FURUTANI ,  Atsushi HIROSE ,  Toshihiko TAKEUCHI

IPC: G01R31/26 ,  G01R31/12

CPC classification number: G01R19/0092

Abstract: A minute current measurement method is provided. In the current measurement method, a first potential is applied to a first terminal of a transistor under test, a second potential is applied to a first terminal of a first transistor, the first transistor is turned on to accumulate a predetermined charge in a node electrically connecting a second terminal of the transistor under test with a second terminal of the first transistor, a third potential of an output terminal of a read circuit electrically connected to the node is measured, the first transistor is turned off, a fourth potential of the output terminal of the read circuit electrically connected to the node is measured, the amount of the charge held by the node is estimated from the amount of change in the potential of the output terminal of the read circuit (e.g., a difference between the third potential and the fourth potential), and a value of current flowing between the first terminal of the transistor under test and the second terminal of the first transistor is calculated from the amount of the charge held by the node.

Abstract translation: 提供了一个微小的电流测量方法。 在当前的测量方法中，将第一电位施加到被测晶体管的第一端，将第二电位施加到第一晶体管的第一端，第一晶体管导通以在节点中积累预定电荷 将被测晶体管的第二端与第一晶体管的第二端连接，测量与节点电连接的读取电路的输出端的第三电位，第一晶体管截止，输出的第四电位 测量与节点电连接的读取电路的端子，根据读取电路的输出端子的电位变化量来估计由节点保持的电荷量（例如，第三电位与 第四电位），并且计算在被测晶体管的第一端子与第一晶体管的第二端子之间流动的电流值 d由节点持有的费用量。

公开(公告)号：US20150179805A1

公开(公告)日：2015-06-25

申请号：US14635199

申请日：2015-03-02

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Masashi TSUBUKU ,  Kengo AKIMOTO ,  Hiroki OHARA ,  Tatsuya HONDA ,  Takatsugu OMATA ,  Yusuke NONAKA ,  Masahiro TAKAHASHI ,  Akiharu MIYANAGA

IPC: H01L29/786 ,  H01L29/10 ,  H01L29/04

CPC classification number: H01L29/78696 ,  H01L29/045 ,  H01L29/1033 ,  H01L29/247 ,  H01L29/7869 ,  H01L29/78693

Abstract: An oxide semiconductor film which has more stable electric conductivity is provided. The oxide semiconductor film comprises a crystalline region. The oxide semiconductor film has a first peak of electron diffraction intensity with a full width at half maximum of greater than or equal to 0.4 nm−1 and less than or equal to 0.7 nm−1 in a region where a magnitude of a scattering vector is greater than or equal to 3.3 nm−1 and less than or equal to 4.1 nm−1. The oxide semiconductor film has a second peak of electron diffraction intensity with a full width at half maximum of greater than or equal to 0.45 nm−1 and less than or equal to 1.4 nm−1 in a region where a magnitude of a scattering vector is greater than or equal to 5.5 nm−1 and less than or equal to 7.1 nm−1.

Abstract translation: 提供了具有更稳定的导电性的氧化物半导体膜。 氧化物半导体膜包含结晶区域。 氧化物半导体膜具有在散射矢量的大小为散射矢量的大小的区域中具有大于或等于0.4nm -1且小于或等于0.7nm -1的半高全宽的电子衍射强度的第一峰值 大于或等于3.3nm -1且小于或等于4.1nm -1。 氧化物半导体膜具有第二峰电子衍射强度，半导体全宽度大于或等于0.45nm-1且小于或等于1.4nm-1，其中散射矢量的大小为 大于或等于5.5nm -1且小于或等于7.1nm -1。

公开(公告)号：US20140246674A1

公开(公告)日：2014-09-04

申请号：US14278634

申请日：2014-05-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Yusuke NONAKA ,  Takayuki INOUE ,  Masashi TSUBUKU ,  Kengo AKIMOTO ,  Akiharu MIYANAGA

IPC: H01L29/786

CPC classification number: H01L29/7869 ,  H01L21/02488 ,  H01L21/02554 ,  H01L21/02565 ,  H01L29/04 ,  H01L29/24 ,  H01L29/78603

Abstract: An object is to provide a semiconductor device including an oxide semiconductor film, which has stable electrical characteristics and high reliability. A stack of first and second material films is formed by forming the first material film (a film having a hexagonal crystal structure) having a thickness of 1 nm to 10 nm over an insulating surface and forming the second material film having a hexagonal crystal structure (a crystalline oxide semiconductor film) using the first material film as a nucleus. As the first material film, a material film having a wurtzite crystal structure (e.g., gallium nitride or aluminum nitride) or a material film having a corundum crystal structure (α-Al2O3, α-Ga2O3, In2O3, Ti2O3, V2O3, Cr2O3, or α-Fe2O3) is used.

Abstract translation: 本发明的目的是提供一种具有稳定的电气特性和高可靠性的氧化物半导体膜的半导体装置。 通过在绝缘表面上形成厚度为1nm至10nm的第一材料膜（具有六方晶体结构的膜）形成第一和第二材料膜的叠层，并形成具有六方晶系结构的第二材料膜（ 使用第一材料膜作为核的结晶氧化物半导体膜）。 作为第一材料膜，具有纤锌矿晶体结构的材料膜（例如氮化镓或氮化铝）或具有刚玉晶体结构的材料膜（α-Al 2 O 3，α-Ga 2 O 3，In 2 O 3，Ti 2 O 3，V 2 O 3，Cr 2 O 3，或 α-Fe 2 O 3）。

公开(公告)号：US20130280857A1

公开(公告)日：2013-10-24

申请号：US13917012

申请日：2013-06-13

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Masashi TSUBUKU ,  Shuhei YOSHITOMI ,  Takahiro TUJI ,  Miyuki HOSOBA ,  Junichiro SAKATA ,  Hiroyuki TOMATSU ,  Masahiko HAYAKAWA

IPC: H01L29/66

CPC classification number: H01L27/1262 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02595 ,  H01L21/02631 ,  H01L21/02667 ,  H01L27/1248 ,  H01L27/127 ,  H01L29/66765 ,  H01L29/66969 ,  H01L29/7869

Abstract: It is an object to provide a manufacturing method of a structure of a thin film transistor including an oxide semiconductor film, in which threshold voltage at which a channel is formed is positive and as close to 0 V as possible. A protective insulating layer is formed to cover a thin film transistor including an oxide semiconductor layer that is dehydrated or dehydrogenated by first heat treatment, and second heat treatment at a temperature that is lower than that of the first heat treatment, in which the increase and decrease in temperature are repeated plural times, is performed, whereby a thin film transistor including an oxide semiconductor layer, in which threshold voltage at which a channel is formed is positive and as close to 0 V as possible without depending on the channel length, can be manufactured.

公开(公告)号：US20240321903A1

公开(公告)日：2024-09-26

申请号：US18678215

申请日：2024-05-30

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Masayuki SAKAKURA ,  Yoshiaki OIKAWA ,  Shunpei YAMAZAKI ,  Junichiro SAKATA ,  Masashi TSUBUKU ,  Kengo AKIMOTO ,  Miyuki HOSOBA

IPC: H01L27/12 ,  G02F1/1343 ,  G02F1/1345 ,  G02F1/1368

CPC classification number: H01L27/124 ,  G02F1/134309 ,  G02F1/13454 ,  G02F1/1368 ,  H01L27/1225 ,  H01L27/1255 ,  G02F2202/10

Abstract: The semiconductor device includes a driver circuit portion including a driver circuit and a pixel portion including a pixel. The pixel includes a gate electrode layer having a light-transmitting property, a gate insulating layer, a source electrode layer and a drain electrode layer each having a light-transmitting property provided over the gate insulating layer, an oxide semiconductor layer covering top surfaces and side surfaces of the source electrode layer and the drain electrode layer and provided over the gate electrode layer with the gate insulating layer therebetween, a conductive layer provided over part of the oxide semiconductor layer and having a lower resistance than the source electrode layer and the drain electrode layer, and an oxide insulating layer in contact with part of the oxide semiconductor layer.

公开(公告)号：US20240038899A1

公开(公告)日：2024-02-01

申请号：US18376994

申请日：2023-10-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Masashi TSUBUKU ,  Hiromichi GODO

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L29/66969

Abstract: It is an object to provide a highly reliable thin film transistor with stable electric characteristics, which includes an oxide semiconductor film. The channel length of the thin film transistor including the oxide semiconductor film is in the range of 1.5 μm to 100 μm inclusive, preferably 3 μm to 10 μm inclusive; when the amount of change in threshold voltage is less than or equal to 3 V, preferably less than or equal to 1.5 V in an operation temperature range of room temperature to 180° C. inclusive or −25° C. to 150° C. inclusive, a semiconductor device with stable electric characteristics can be manufactured. In particular, in a display device which is an embodiment of the semiconductor device, display unevenness due to variation in threshold voltage can be reduced.