利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

29 条记录 (耗时 0.024 秒)

    Method and apparatus for avoiding gated diode breakdown in transistor circuits
    23.
    发明授权
    Method and apparatus for avoiding gated diode breakdown in transistor circuits 有权
    用于避免晶体管电路中栅极二极管击穿的方法和装置

    公开(公告)号：US07132873B2

    公开(公告)日：2006-11-07

    申请号：US10338551

    申请日：2003-01-08

    申请人： Shane C. Hollmer

    发明人： Shane C. Hollmer

    IPC分类号： H03K5/08

    CPC分类号： H01L27/0266

    摘要： An N-channel transistor protection circuit and method are disclosed that prevent gated diode breakdown in N-channel transistors that have a high voltage on their drain. The disclosed N-channel protection circuit may be switched in a high voltage mode between a high voltage level and a lower rail voltage. A high voltage conversion circuit prevents gated diode breakdown in N-channel transistors by dividing the high voltage across two N-channel transistors, MXU0 and MXU1, such that no transistor exceeds the breakdown voltage, Vbreakdown. An intermediate voltage drives the top N-channel transistor, MXU0. The top N-channel transistor, MXU0, is gated with a voltage level that is at least one N-channel threshold, Vtn, below the high voltage level, Vep, using the intermediate voltage level, nprot. The drain voltage of MXU0 will be at least one N-channel threshold, Vtn, lower than the input voltage level, nprot, and the drain voltage Vd of the bottom N-channel transistor, MXU1, is limited to less than the breakdown voltage, Vbreakdown.

    摘要翻译： 公开了一种N沟道晶体管保护电路和方法，其防止在其漏极上具有高电压的N沟道晶体管中门控二极管击穿。 所公开的N沟道保护电路可以在高电压电平和较低电压电压之间的高电压模式下切换。 高电压转换电路通过将两个N沟道晶体管MXU0和MXU1之间的高电压分压来防止N沟道晶体管中的栅极二极管击穿，使得没有晶体管超过击穿电压，V < 。 中间电压驱动顶部的N沟道晶体管MXU 0。 顶部的N沟道晶体管MXU 0被门控，其电压电平至少为低于高电压电平V SUB的至少一个N沟道阈值V IN Tn ，使用中间电压电平，nprot。 MXU 0的漏极电压将至少比N输入电压电平NOUT和漏极电压V SUB小于N个通道阈值V SUB， 底部N沟道晶体管MXU 1被限制为小于击穿电压V分压。

    Double boosting scheme for NAND to improve program inhibit characteristics
    25.
    发明授权
    Double boosting scheme for NAND to improve program inhibit characteristics 有权
    NAND的双升压方案，提高程序抑制特性

    公开(公告)号：US06504757B1

    公开(公告)日：2003-01-07

    申请号：US09922415

    申请日：2001-08-03

    申请人： Shane C. Hollmer ,  Pau-Ling Chen ,  Quang Binh

    发明人： Shane C. Hollmer ,  Pau-Ling Chen ,  Quang Binh

    IPC分类号： G11C1604

    CPC分类号： G11C16/0483 ,  G11C16/10

    摘要： A method for boosting potential in the channel of unselected memory cells on a selected bit-line. In this method, a first voltage is applied to all the word-lines of the memory cells in the string. A second voltage is then applied to word-lines adjacent the selected word lines to isolate the selected memory cell. Next, a programming voltage is applied to the selected word-line. In one embodiment, a time delay is applied between applying the second voltage and applying the third voltages to ensure isolation of the selected memory cell before applying the third voltage.

    摘要翻译： 一种用于在所选位线上提升未选择存储单元的通道中的电位的方法。 在该方法中，对串中的存储单元的所有字线施加第一电压。 然后将第二电压施加到与所选字线相邻的字线，以隔离所选择的存储单元。 接下来，将编程电压施加到所选择的字线。 在一个实施例中，在施加第二电压和施加第三电压之间施加时间延迟，以确保在施加第三电压之前所选择的存储器单元的隔离。

    Continuous capacitor divider sampled regulation scheme
    26.
    发明授权
    Continuous capacitor divider sampled regulation scheme 有权
    连续电容分压器采样调节方案

    公开(公告)号：US06411069B1

    公开(公告)日：2002-06-25

    申请号：US09387018

    申请日：1999-08-31

    申请人： Shane C. Hollmer

    发明人： Shane C. Hollmer

    IPC分类号： G05F140

    CPC分类号： G11C5/145 ,  H02M3/073

    摘要： A refresh mechanism refreshes a supplied capacitor of a capacitor divider circuit at an interval that keeps an amount of charge degradation at a coupled up capacitor to less than a predetermined threshold. A node between the supplied capacitor and the coupled up capacitor provides a voltage sampling node having a divided voltage. Timing for the refresh operations may be established via internal clocks or internal oscillators running at multiples of other circuits already internal to the device utilizing the divided voltage. The divided voltage is then utilized for comparison, feedback (voltage regulation, for example), or other purposes. The invention is applicable to all types of circuits where degradation occurs due any type of leakage or other permutations affecting circuit operations.

    摘要翻译： 刷新机构以一定间隔刷新电容分压器电路的电容器，使得耦合上拉电容器的电荷劣化量小于预定阈值。 所提供的电容器和耦合上拉电容器之间的节点提供具有分压的电压采样节点。 用于刷新操作的时序可以通过内部时钟或内部振荡器建立，该时钟或内部振荡器利用已分压的电压在设备内部的其他电路的倍数运行。 然后将分压电压用于比较，反馈（例如电压调节）或其他目的。 本发明适用于所有类型的电路，其中由于任何类型的泄漏或影响电路操作的其它排列而发生劣化。

    EEPROM decoder block having a p-well coupled to a charge pump for charging the p-well and method of programming with the EEPROM decoder block
    27.
    发明授权
    EEPROM decoder block having a p-well coupled to a charge pump for charging the p-well and method of programming with the EEPROM decoder block 有权
    EEPROM解码器块具有耦合到用于对p阱充电的电荷泵的p阱以及用EEPROM解码器块进行编程的方法

    公开(公告)号：US6081455A

    公开(公告)日：2000-06-27

    申请号：US232023

    申请日：1999-01-14

    申请人： Binh Q. Le ,  Pau-ling Chen ,  Shane C. Hollmer

    发明人： Binh Q. Le ,  Pau-ling Chen ,  Shane C. Hollmer

    IPC分类号： G11C8/12 ,  G11C16/08 ,  G11C16/12 ,  G11C16/00

    CPC分类号： G11C8/12 ,  G11C16/08 ,  G11C16/12

    摘要： A block decoder includes a p-well. A low voltage source is coupled to the p-well for asserting a body bias voltage to the p-well. An n-type word line pass transistor is positioned within the p-well and is coupled to a word line for passing programming voltages to the word line. A high voltage source is coupled to pass circuitry configured to assert a voltage on a gate of the pass transistor. The low voltage source is configured to apply a voltage of approximately 10 volts or more to the p-well during programming, thus reducing the voltage between the source and body region (and thus the threshold voltage as well) of NMOS transistors disposed within the p-well. Therefore, the amount of voltage needed to be applied to the pass transistors is reduced. Furthermore, the pass circuitry can work for lower supply voltages since the supply voltage is limited by the threshold voltage of the n-type transistors within the p-well.

    摘要翻译： 块解码器包括p阱。 低电压源耦合到p阱，用于断定对p阱的体偏置电压。 n型字线传输晶体管位于p阱内并耦合到字线，用于将编程电压传递到字线。 耦合高电压源以通过配置成断定传输晶体管的栅极上的电压的电路。 低电压源被配置为在编程期间向p阱施加大约10伏特或更高的电压，从而降低位于p内的NMOS晶体管的源极和体区之间的电压（以及阈值电压） -好。 因此，需要施加到传输晶体管的电压量减小。 此外，通过电路可以用于较低的电源电压，因为电源电压受p阱内n型晶体管的阈值电压的限制。

    Multistepped threshold convergence for a flash memory array
    28.
    发明授权
    Multistepped threshold convergence for a flash memory array 失效
    闪存阵列的多级阈值收敛

    公开(公告)号：US5576991A

    公开(公告)日：1996-11-19

    申请号：US269540

    申请日：1994-07-01

    申请人： Nader Radjy ,  Lee E. Cleveland ,  Jian Chen ,  Shane C. Hollmer

    发明人： Nader Radjy ,  Lee E. Cleveland ,  Jian Chen ,  Shane C. Hollmer

    IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/16 ,  G11C16/34 ,  G11C11/40

    CPC分类号： G11C16/3409 ,  G11C16/16 ,  G11C16/3404

    摘要： A method of converging threshold voltages of memory cells in a flash EEPROM array after the memory cells have been erased, the method including applying a gate voltage having an initial negative value which is increased to a more positive value in steps during application of a drain disturb voltage. By applying a gate voltage with an initial negative value, leakage current during convergence is reduced enabling all cells on bit lines of the array to be converged in parallel.

    摘要翻译： 一种在存储器单元被擦除之后在闪存EEPROM阵列中会聚存储器单元的阈值电压的方法，该方法包括在施加漏极干扰期间施加具有初始负值的栅极电压，其逐步增加到更多的正值 电压。 通过施加具有初始负值的栅极电压，减小了会聚期间的漏电流，使得阵列的位线上的所有单元能够并行收敛。

    Boosted and regulated gate power supply with reference tracking for multi-density and low voltage supply memories
    29.
    发明授权
    Boosted and regulated gate power supply with reference tracking for multi-density and low voltage supply memories 失效
    增强和调节的门电源，具有多密度和低电压电源存储器的参考跟踪

    公开(公告)号：US5511026A

    公开(公告)日：1996-04-23

    申请号：US160578

    申请日：1993-12-01

    申请人： Lee E. Cleveland ,  Shane C. Hollmer

    发明人： Lee E. Cleveland ,  Shane C. Hollmer

    IPC分类号： G11C17/00 ,  G11C11/56 ,  G11C16/02 ,  G11C16/06 ,  G11C16/08 ,  G11C16/30 ,  H01L21/822 ,  H01L27/04 ,  G11C7/00 ,  H03L1/00

    CPC分类号： G11C11/5621 ,  G11C16/08 ,  G11C16/30 ,  G11C5/145 ,  G11C8/14

    摘要： A gate power supply for supplying power to the gates of flash EEPROM memory cells in a multi-density or low voltage supply memory array to determine the states stored by the memory cells. The gate power supply includes a multi-phase voltage pump to increase voltage supplied to the gates of the memory cells above a system voltage supply, V.sub.CC to increase the working margin between memory cell states. The gate power supply further includes a low power supply standby pump to maintain the boosted voltage during an inactive mode. The wordline decoder for the memory is divided into sections with a large n-well parasitic capacitance of each decoder section acting as a reservoir to store the charge supplied by the low power standby pump. In an active mode, the parasitic capacitance in unselected decoder sections supplies power to the input of the selected diecoder section while the multi-phase pump is turning on. Zener regulation diodes are coupled to the inputs of each decoder section to regulate the voltage supplied to each section. A reference supply feeds back power from the input of the selected decoder section to the input of a reference array. The reference supply further provides circuitry to reduce mismatches between the memory array and the reference array.

    摘要翻译： 一种用于向多密度或低电压电源存储器阵列中的快速EEPROM存储单元的栅极供电以确定存储单元存储的状态的栅极电源。 栅极电源包括多相电压泵，以增加提供给系统电压源上方的存储器单元的栅极的电压，以增加存储单元状态之间的工作裕度。 栅极电源还包括低功率备用泵，以在非活动模式期间维持升压电压。 用于存储器的字线解码器被分成具有作为存储器的每个解码器部分的大n阱寄生电容的部分，以存储由低功率备用泵提供的电荷。 在活动模式中，未选择解码器部分中的寄生电容在多相泵接通时向所选择的解码器部分的输入端供电。 齐纳调节二极管耦合到每个解码器部分的输入以调节提供给每个部分的电压。 参考电源将功率从所选择的解码器部分的输入反馈到参考阵列的输入。 参考电源还提供减少存储器阵列和参考阵列之间不匹配的电路。