公开(公告)号：US06406956B1

公开(公告)日：2002-06-18

申请号：US09845483

申请日：2001-04-30

申请人： Ming-Hsing Tsai ,  Chii-Ming Wu

发明人： Ming-Hsing Tsai ,  Chii-Ming Wu

IPC分类号： H01L218238

CPC分类号： H01L27/0629 ,  H01L28/20 ,  H01L29/66545

摘要： A layer of gate oxide and polysilicon are deposited over the surface of a substrate, these layers are etched to create a dummy gate and a resistor. Spacers are formed on the dummy gate and the resistor, suitable impurities are implanted self-aligned with the dummy gate. A layer of dielectric is deposited and polished down to the surface of the dummy gate and the polysilicon resistor, the dummy gate is removed creating an opening in the layer of dielectric. A high-k dielectric is deposited over which a layer of metal is deposited, the surface of the layer of metal and high-k dielectric are polished down to the surface of the layer of dielectric leaving in place a metal gate electrode and a polysilicon resistor.

摘要翻译： 在衬底的表面上沉积一层栅极氧化物和多晶硅，蚀刻这些层以产生伪栅极和电阻器。 间隔物形成在虚拟栅极和电阻器上，合适的杂质被注入与伪栅极自对准。 电介质层沉积并抛光到虚拟栅极和多晶硅电阻器的表面，去除伪栅极，在电介质层中形成开口。 沉积高k电介质，在其上沉积金属层，金属层和高k电介质的表面被抛光到介电层的表面，留下原位金属栅电极和多晶硅电阻 。

公开(公告)号：US06399486B1

公开(公告)日：2002-06-04

申请号：US09442313

申请日：1999-11-22

申请人： Sheng-Hsiung Chen ,  Ming-Hsing Tsai

发明人： Sheng-Hsiung Chen ,  Ming-Hsing Tsai

IPC分类号： H01L2144

CPC分类号： H01L21/2885 ,  H01L21/76882

摘要： The present invention teaches a special annealing process to “heal” electrochemical copper deposited (ECD) defects in a dual damascene via and trench structure. The annealing step is processed after the electrochemical deposition (ECD) of the top excess copper and before the chemical mechanical polishing (CMP) of the copper. The key processing steps of this invention are the special annealing steps at key temperatures, ambient, pressures and times to anneal out the defective copper voids in the dual damascene structure. These annealing conditions are special annealing steps to promote low temperature copper surface diffusion to “heal” the voids and other defectives within the copper trench and via structure. The special annealing conditions of: temperature, ambient, pressure and time are the following: temperature in a range of about 300 to 500° C., ambient of nitrogen N2, hydrogen H2 gases (reducing atmosphere to remove copper oxide, N2/H2 plasma preferred), pressure in a range of about 100 MPa to 600 MPa, time in a range of about 0.5 to 10 minutes. These conditions are designed to take advantage of low temperature surface diffusion mechanisms.

摘要翻译： 本发明教导了一种特殊的退火方法，以在“双镶嵌”通孔和沟槽结构中“治愈”电化学铜沉积（ECD）缺陷。 退火步骤在顶部多余铜的电化学沉积（ECD）和铜的化学机械抛光（CMP）之前进行。 本发明的关键处理步骤是关键温度，环境温度，压力和退出双镶嵌结构中缺陷铜空隙的时间的特殊退火步骤。 这些退火条件是促进低温铜表面扩散以“愈合”铜沟槽和通孔结构内的空隙和其它缺陷的特殊退火步骤。 温度，环境温度，压力和时间的特殊退火条件如下：温度在约300至500℃的范围内，氮气环境N2，氢气H 2气体（还原气氛以除去氧化铜，N 2 / H 2等离子体 优选），压力在约100MPa至600MPa的范围内，时间在约0.5至10分钟的范围内。 这些条件被设计为利用低温表面扩散机制。

公开(公告)号：US06319831B1

公开(公告)日：2001-11-20

申请号：US09507904

申请日：2000-02-22

申请人： Wen-Jye Tsai ,  Ming-Hsing Tsai

发明人： Wen-Jye Tsai ,  Ming-Hsing Tsai

IPC分类号： H01L2144

CPC分类号： H01L21/2885 ,  H01L21/76877

摘要： A multi-step electrochemical method for forming a copper metallurgy on an integrated circuit which has high aspect ratio contact/via openings is described. The method is designed to give good coverage and gap filling capability as well as high production throughput by depositing the copper in two stages with an optional dwell period between the stages. The process utilizes a copper plating electrolyte which contains an added brighteners and levelers. A first copper layer is plated at a low current density which provides good coverage resulting from a high throwing power. The high aspect ratio openings are covered with a substantial thickness of a uniform, high quality copper coating. During plating, the concentration of brightener becomes depleted in the base region of high aspect ratio contacts or vias. Optionally, the brightener is replenished in these regions during a brief dwell period wherein the plating current is stopped. Next, a high current density is applied whereby the openings are filled and additional copper is deposited over them at a high deposition rate. A benefit of the high current density deposition is that depletion of leveler chemical in the openings enhances the growth rate of copper at the base of the openings thereby favoring growth from bottom up. This avoids the formation of voids in the openings. The greatest throughput benefits are realized, by way of the high current density step, when the process is applied to the formation of a dual damascene metallurgy.

摘要翻译： 描述了在具有高纵横比接触/通孔开口的集成电路上形成铜冶金的多步电化学方法。 该方法设计为通过在两个阶段之间以可选的停留时间两段沉积铜来提供良好的覆盖和间隙填充能力以及高的生产量。 该方法使用含有添加的增白剂和矫光剂的镀铜电解质。 第一铜层以低电流密度电镀，由高投掷功率提供良好的覆盖。 高长宽比的开口用相当厚度的均匀的高质量铜涂层覆盖。 在电镀期间，增亮剂的浓度在高纵横比触点或通孔的基极区域中耗尽。 任选地，在电镀电流停止的短暂停留期间，增白剂在这些区域中补充。 接下来，施加高电流密度，由此填充开口并且以高沉积速率在其上沉积附加的铜。 高电流密度沉积的益处在于开口中矫正剂化学品的消耗增加了开口底部的铜的生长速率，从而有利于从下到上生长。 这避免了在开口中形成空隙。 通过高电流密度步骤，当该方法应用于双镶嵌冶金的形成时，实现了最大的生产效率。

公开(公告)号：US06274484B1

公开(公告)日：2001-08-14

申请号：US09527184

申请日：2000-03-17

申请人： Ming-Hsing Tsai ,  Sheng-Hsiung Cheu

发明人： Ming-Hsing Tsai ,  Sheng-Hsiung Cheu

IPC分类号： H01L214763

CPC分类号： H01L21/76886 ,  H01L21/28079 ,  H01L29/66545

摘要： A process for forming a low resistivity tungsten layer, for use as a metal gate structure, or a metal damascene structure, has been developed. The process features initial deposition of a metastable tungsten nitride layer, via a plasma enhanced, or metal organic chemical vapor deposition procedures, resulting in good adhesion, in addition to good step coverage, of the tungsten nitride layer, to underlying or adjacent insulator layers. The high resistivity, tungsten nitride layer is then converted to a lower resistivity tungsten layer, via a rapid thermal anneal procedure, performed in an argon ambient, or in vacuum.

摘要翻译： 已经开发了用于形成用作金属栅极结构的低电阻率钨层或金属镶嵌结构的工艺。 该方法特征在于通过等离子体增强或金属有机化学气相沉积方法初始沉积亚稳态氮化钨层，除了氮化钨层的良好的步骤覆盖之外，还可以向下面或相邻的绝缘体层提供良好的附着力。 然后通过快速热退火工艺将高电阻率的氮化钨层转化为较低电阻率的钨层，在氩气环境或真空中进行。

公开(公告)号：US09269612B2

公开(公告)日：2016-02-23

申请号：US13434691

申请日：2012-03-29

申请人： Chien-An Chen ,  Wen-Jiun Liu ,  Chun-Chieh Lin ,  Hung-Wen Su ,  Ming-Hsing Tsai ,  Syun-Ming Jang

发明人： Chien-An Chen ,  Wen-Jiun Liu ,  Chun-Chieh Lin ,  Hung-Wen Su ,  Ming-Hsing Tsai ,  Syun-Ming Jang

IPC分类号： H01L21/768 ,  H01L23/532

CPC分类号： H01L21/76877 ,  H01L21/76802 ,  H01L21/76819 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76847 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76864 ,  H01L21/76882 ,  H01L21/76886 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure includes a first trench and a second trench. The second trench is wider than the first trench. Both trenches are lined with a diffusion barrier layer, and a first conductive layer is deposited over the diffusion barrier layer. A metal cap layer is deposited over the first conductive layer. A second conductive layer is deposited over the metal cap layer in the second trench.

摘要翻译： 互连结构包括第一沟槽和第二沟槽。 第二沟槽比第一沟槽宽。 这两个沟槽都带有扩散阻挡层，并且第一导电层沉积在扩散阻挡层上。 在第一导电层上沉积金属覆盖层。 第二导电层沉积在第二沟槽中的金属覆盖层上。

公开(公告)号：US09123781B2

公开(公告)日：2015-09-01

申请号：US12787559

申请日：2010-05-26

申请人： Hung-Wen Su ,  Shih-Wei Chou ,  Ming-Hsing Tsai

发明人： Hung-Wen Su ,  Shih-Wei Chou ,  Ming-Hsing Tsai

IPC分类号： H01L21/00 ,  H01L21/768 ,  H01L21/285

CPC分类号： H01L23/528 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76888 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor devices and methods for forming the same in which damages to a low-k dielectric layer therein can be reduced or even prevented are provided. A semiconductor device is provided, comprising a substrate. A dielectric layer with at least one conductive feature therein overlies the substrate. An insulating cap layer overlies the top surface of the low-k dielectric layer adjacent to the conductive feature, wherein the insulating cap layer comprises metal ions.

摘要翻译： 提供了可以减少或甚至防止对其中低k电介质层的损坏的用于形成其的半导体器件及其制造方法。 提供了一种半导体器件，包括衬底。 其中具有至少一个导电特征的电介质层覆盖在衬底上。 绝缘覆盖层覆盖邻近导电特征的低k电介质层的顶表面，其中绝缘帽层包括金属离子。

公开(公告)号：US08053892B2

公开(公告)日：2011-11-08

申请号：US11341827

申请日：2006-01-27

申请人： Ting-Chu Ko ,  Ming-Hsing Tsai ,  Chien-Hsueh Shih

发明人： Ting-Chu Ko ,  Ming-Hsing Tsai ,  Chien-Hsueh Shih

IPC分类号： H01L23/48

CPC分类号： H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and system is provided for efficiently varying the composition of the metal interconnects for a semiconductor device. A metal interconnect according to the present disclosure has an intermediate layer on a dielectric material, the intermediate layer having a relatively higher concentration of an impurity metal along with a primary metal, the impurity metal having a lower reduction potential than the primary metal. The metal interconnect has a main layer of the metal alloy interconnect on top of the intermediate layer and surrounded by the intermediate layer, the main layer having a relatively higher concentration of the primary metal than the intermediate layer, wherein the intermediate and main layers of the metal alloy interconnect each maintains a material uniformity.

摘要翻译： 提供了一种方法和系统，用于有效地改变半导体器件的金属互连的组成。 根据本公开的金属互连在电介质材料上具有中间层，中间层与主金属一起具有较高浓度的杂质金属，杂质金属具有比初级金属低的还原电位。 金属互连件在中间层的顶部具有金属合金互连的主层，被中间层包围，主层具有比中间层更高的一次金属浓度，其中，中间层和中间层的中间层和主要层 金属合金互连件均保持材料均匀性。

公开(公告)号：US07476306B2

公开(公告)日：2009-01-13

申请号：US10814175

申请日：2004-04-01

申请人： Hung-Wen Su ,  Chien-Hsueh Shih ,  Ming-Hsing Tsai

发明人： Hung-Wen Su ,  Chien-Hsueh Shih ,  Ming-Hsing Tsai

IPC分类号： C25D17/02

CPC分类号： H01L21/2885 ,  C25D7/123 ,  C25D17/001 ,  C25D17/02 ,  C25D21/02

摘要： Apparatus and method for metal electroplating. The apparatus for metal electroplating includes an electroplating tank for containing an electrolyte at a first temperature, a substrate holder for holding a semiconductor substrate, and a heater for heating the portion of the electrolyte adjacent to the substrate holder to a second temperature higher than the first temperature.

摘要翻译： 金属电镀设备及方法 用于金属电镀的设备包括用于在第一温度下容纳电解质的电镀槽，用于保持半导体衬底的衬底保持器和用于将邻近衬底保持器的部分电解质加热至高于第一温度的第二温度的加热器 温度。

公开(公告)号：US07312531B2

公开(公告)日：2007-12-25

申请号：US11261200

申请日：2005-10-28

申请人： Hui-Lin Chang ,  Yung-Cheng Lu ,  Chung-Chi Ko ,  Pi-Tsung Chen ,  Shau-Lin Shue ,  Chien-Hsueh Shih ,  Hung-Wen Su ,  Ming-Hsing Tsai

发明人： Hui-Lin Chang ,  Yung-Cheng Lu ,  Chung-Chi Ko ,  Pi-Tsung Chen ,  Shau-Lin Shue ,  Chien-Hsueh Shih ,  Hung-Wen Su ,  Ming-Hsing Tsai

IPC分类号： H01L29/40 ,  H01L21/44

CPC分类号： H01L23/53276 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76879 ,  H01L21/76885 ,  H01L23/5226 ,  H01L2221/1094 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor devices and methods for fabricating the same. The devices include a substrate, a catalyst layer, a second dielectric layer, and carbon nanotubes (CNTs). The substrate comprises an overlying first dielectric layer with an electrode embedded therein. The catalyst layer overlies the electrode and the first dielectric layer and substantially comprises Co and M1, wherein M1 is selected from a group consisting of W, P, B, Bi, Ni, and a combination thereof. The second dielectric layer overlies the catalyst layer and comprises an opening exposing parts of the catalyst layer. The carbon nanotubes (CNTs) are disposed on the exposed catalyst layer and electrically connect the electrode.

公开(公告)号：US20070181434A1

公开(公告)日：2007-08-09

申请号：US11783245

申请日：2007-04-06

申请人： Hsien-Ming Lee ,  Jing-Cheng Lin ,  Shing-Chyang Pan ,  Ming-Hsing Tsai ,  Hung-Wen Su ,  Shih-Wei Chou ,  Shau-Lin Shue ,  Kuo-Wei Cheng ,  Ting-Chu Ko

发明人： Hsien-Ming Lee ,  Jing-Cheng Lin ,  Shing-Chyang Pan ,  Ming-Hsing Tsai ,  Hung-Wen Su ,  Shih-Wei Chou ,  Shau-Lin Shue ,  Kuo-Wei Cheng ,  Ting-Chu Ko

IPC分类号： C25D5/34 ,  H01L21/44 ,  C25D3/38

CPC分类号： H01L21/2885 ,  H01L21/76843 ,  H01L21/76861 ,  H01L21/76862 ,  H01L21/76873 ,  H01L21/76877

摘要： A method of electrochemical deposition (ECD) provides a barrier and a seed layer on a substrate. The surfaces of the substrate are pre-treated before a metal layer is electrochemically deposited thereon in an electrochemical plating cell with a physical or a chemical surface treatment process. The electrochemical plating cell is covered by a cap to prevent evaporation of the electrolyte solution. The electrochemical plating cell includes a substrate holder assembly with a lift seal, e.g., with a contact angle θ less than 90° between the lift seal and the substrate. The substrate holder assembly includes a substrate chuck at the rear side of the substrate.

摘要翻译： 电化学沉积（ECD）的方法在衬底上提供阻挡层和种子层。 在将金属层电化学沉积在具有物理或化学表面处理工艺的电化学镀覆电池中之前，对基板的表面进行预处理。 电化学镀覆电池被盖覆盖以防止电解质溶液的蒸发。 电化学电镀单元包括具有提升密封件的衬底保持器组件，例如在提升密封件和衬底之间的接触角θ小于90°。 衬底保持器组件包括在衬底的后侧的衬底卡盘。