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    FABRICATION METHOD AND STRUCTURE OF SEMICONDUCTOR NON-VOLATILE MEMORY DEVICE
    21.
    发明申请
    FABRICATION METHOD AND STRUCTURE OF SEMICONDUCTOR NON-VOLATILE MEMORY DEVICE 有权
    半导体非易失性存储器件的制造方法和结构

    公开(公告)号：US20100135080A1

    公开(公告)日：2010-06-03

    申请号：US12648796

    申请日：2009-12-29

    申请人： Digh HISAMOTO ,  Shinichiro Kimura ,  Kan Yasui ,  Nozomu Matsuzaki

    发明人： Digh HISAMOTO ,  Shinichiro Kimura ,  Kan Yasui ,  Nozomu Matsuzaki

    IPC分类号： G11C16/04 ,  H01L29/792

    CPC分类号： H01L27/11531 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/792

    摘要： A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The memory gate is adjacent to the selection gate via the laminated film. In the regions on both sides of the selection gate and the memory gate in the p-type well, n-type impurity diffusion layers serving as the source and drain are formed. The region controlled by the selection gate and the region controlled by the memory gate located in the channel region between said impurity diffusion layers have the different charge densities of the impurity from each other.

    摘要翻译： 提供具有良好写入/擦除特性的非易失性半导体存储器件。 通过栅极绝缘体在半导体衬底的p型阱上形成选择栅极，并且通过由氧化硅膜，氮化硅膜和氮化硅膜构成的层叠膜在p型阱上形成存储栅极 氧化硅膜。 存储器栅极通过层叠膜与选择栅极相邻。 在p型阱中的选择栅极和存储栅极的两侧的区域中，形成用作源极和漏极的n型杂质扩散层。 由选择栅极控制的区域和由位于所述杂质扩散层之间的沟道区域中的存储栅极控制的区域具有彼此不同的杂质的电荷密度。

    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
    23.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20100084709A1

    公开(公告)日：2010-04-08

    申请号：US11993862

    申请日：2006-06-30

    申请人： Ryuta Tsuchiya ,  Shinichiro Kimura

    发明人： Ryuta Tsuchiya ,  Shinichiro Kimura

    IPC分类号： H01L29/786 ,  H01L21/336 ,  H01L21/86

    CPC分类号： H01L27/12 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/0922 ,  H01L27/1207

    摘要： When a bulk silicon substrate and an SOI substrate are used separately, a board area is increased and so it is impossible to reduce the size of a semiconductor device as a whole. On the other hand, when an SOI-type MISFET and a bulk-type MISFET are formed on a same substrate, the SOI-type MISFET and the bulk-type MISFET should be formed in separate steps respectively, and thus the process gets complicated. A single crystal semiconductor substrate and an SOI substrate separated from the single crystal semiconductor substrate by a thin buried insulating film and having a thin single crystal semiconductor thin film (SOI layer) are used, and well diffusion layer regions, drain regions, gate insulating films and gate electrodes of the SOI-type MISFET and the bulk-type MISFET are formed in same steps. Since the bulk-type MISFET and the SOI-type MISFET can be formed on the same substrate, the board area can be reduced. A simple process can be realized by making manufacturing steps of the SOI-type MISFET and the bulk-type MISFET common.

    摘要翻译： 当单独使用体硅衬底和SOI衬底时，板面积增加，因此整体上不可能减小半导体器件的尺寸。 另一方面，当在同一衬底上形成SOI型MISFET和体型MISFET时，分别将SOI型MISFET和体型MISFET分别形成，因此工艺变得复杂。 使用通过薄埋入绝缘膜与单晶半导体衬底分离并具有薄单晶半导体薄膜（SOI层）的单晶半导体衬底和SOI衬底，以及良好扩散层区域，漏极区域，栅极绝缘膜 并且以相同的步骤形成SOI型MISFET和体型MISFET的栅电极。 由于可以在同一基板上形成体型MISFET和SOI型MISFET，所以可以减小电路板面积。 可以通过制造SOI型MISFET和体型MISFET的制造步骤来实现简单的工艺。

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    24.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20080258218A1

    公开(公告)日：2008-10-23

    申请号：US12105226

    申请日：2008-04-17

    申请人： Yusuke Morita ,  Yoshinobu Kimura ,  Ryuta Tsuchiya ,  Nobuyuki Sugii ,  Shinichiro Kimura

    发明人： Yusuke Morita ,  Yoshinobu Kimura ,  Ryuta Tsuchiya ,  Nobuyuki Sugii ,  Shinichiro Kimura

    IPC分类号： H01L27/01

    CPC分类号： H01L29/045 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7834

    摘要： A MIS transistor having an inclined stacked source/drain structure increased in speed is provided. The MIS transistor comprises: a gate electrode formed on a substrate; a first sidewall insulating film formed on the substrate and along a sidewall of the gate electrode; source/drain semiconductor regions formed on a main surface of the substrate and respectively having one edge positioned under the sidewall of the gate electrode; a first stacked layer formed on the source/drain semiconductor regions and in contact with the first sidewall insulating film; a second sidewall insulating film formed on the stacked layer and in contact with the first sidewall insulating film; and a second stacked layer formed on the first stacked layer and in contact with the second sidewall insulating layer.

    摘要翻译： 提供了具有倾斜堆叠的源极/漏极结构的MIS晶体管，其速度提高。 MIS晶体管包括：形成在衬底上的栅电极; 形成在所述基板上并沿着所述栅电极的侧壁的第一侧壁绝缘膜; 源极/漏极半导体区域，形成在基板的主表面上，并且分别具有位于栅电极的侧壁下方的一个边缘; 形成在所述源极/漏极半导体区域上并与所述第一侧壁绝缘膜接触的第一堆叠层; 形成在所述层叠层上并与所述第一侧壁绝缘膜接触的第二侧壁绝缘膜; 以及形成在第一堆叠层上并与第二侧壁绝缘层接触的第二堆叠层。

    Fabrication method and structure of semiconductor non-volatile memory device
    26.
    发明申请
    Fabrication method and structure of semiconductor non-volatile memory device 有权
    半导体非易失性存储器件的制造方法和结构

    公开(公告)号：US20070040208A1

    公开(公告)日：2007-02-22

    申请号：US11589095

    申请日：2006-10-30

    申请人： Digh Hisamoto ,  Shinichiro Kimura ,  Kan Yasui ,  Nozomu Matsuzaki

    发明人： Digh Hisamoto ,  Shinichiro Kimura ,  Kan Yasui ,  Nozomu Matsuzaki

    IPC分类号： H01L29/76

    CPC分类号： H01L27/11531 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/792

    摘要： A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The memory gate is adjacent to the selection gate via the laminated film. In the regions on both sides of the selection gate and the memory gate in the p-type well, n-type impurity diffusion layers serving as the source and drain are formed. The region controlled by the selection gate and the region controlled by the memory gate located in the channel region between said impurity diffusion layers have the different charge densities of the impurity from each other.

    摘要翻译： 提供具有良好写入/擦除特性的非易失性半导体存储器件。 通过栅极绝缘体在半导体衬底的p型阱上形成选择栅极，并且通过由氧化硅膜，氮化硅膜和氮化硅膜构成的层叠膜在p型阱上形成存储栅极 氧化硅膜。 存储器栅极通过层叠膜与选择栅极相邻。 在p型阱中的选择栅极和存储栅极的两侧的区域中，形成用作源极和漏极的n型杂质扩散层。 由选择栅极控制的区域和由位于所述杂质扩散层之间的沟道区域中的存储栅极控制的区域具有彼此不同的杂质的电荷密度。

    Fabrication method and structure of semiconductor non-volatile memory device
    27.
    发明授权
    Fabrication method and structure of semiconductor non-volatile memory device 有权
    半导体非易失性存储器件的制造方法和结构

    公开(公告)号：US07132718B2

    公开(公告)日：2006-11-07

    申请号：US10726507

    申请日：2003-12-04

    申请人： Digh Hisamoto ,  Shinichiro Kimura ,  Kan Yasui ,  Nozomu Matsuzaki

    发明人： Digh Hisamoto ,  Shinichiro Kimura ,  Kan Yasui ,  Nozomu Matsuzaki

    IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC分类号： H01L27/11531 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/792

    摘要： A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The memory gate is adjacent to the selection gate via the laminated film. In the regions on the both sides of the selection gate and the memory gate in the p-type well, n-type impurity diffusion layers serving as the source and drain are formed. The region controlled by the selection gate and the region controlled by the memory gate located in the channel region between said impurity diffusion layers have the different charge densities of the impurity from each other.

    摘要翻译： 提供具有良好写入/擦除特性的非易失性半导体存储器件。 通过栅极绝缘体在半导体衬底的p型阱上形成选择栅极，并且通过由氧化硅膜，氮化硅膜和氮化硅膜构成的层叠膜在p型阱上形成存储栅极 氧化硅膜。 存储器栅极通过层叠膜与选择栅极相邻。 在选择栅极的两侧的区域和p型阱的存储栅极中，形成用作源极和漏极的n型杂质扩散层。 由选择栅极控制的区域和由位于所述杂质扩散层之间的沟道区域中的存储栅极控制的区域具有彼此不同的杂质的电荷密度。