公开(公告)号：US20140332976A1

公开(公告)日：2014-11-13

申请号：US14013420

申请日：2013-08-29

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yan-Heng Chen ,  Chun-Tang Lin ,  Yan-Yi Liao ,  Hung-Wen Liu ,  Chieh-Yuan Chi ,  Hsi-Chang Hsu

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L25/50 ,  H01L21/4846 ,  H01L21/486 ,  H01L21/568 ,  H01L21/768 ,  H01L21/76877 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06558 ,  H01L2924/12042 ,  H01L2924/15156 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/3511 ,  H01L2224/82 ,  H01L2224/83 ,  H01L2924/00

Abstract: A semiconductor package is disclosed, which includes: a carrier having at least an opening; a plurality of conductive traces formed on the carrier and in the opening; a first semiconductor element disposed in the opening and electrically connected to the conductive traces; a second semiconductor element disposed on the first semiconductor element in the opening; and a redistribution layer structure formed on the carrier and the second semiconductor element for electrically connecting the conductive traces and the second semiconductor element. Since the semiconductor elements are embedded and therefore positioned in the opening of the carrier, the present invention eliminates the need to perform a molding process before forming the redistribution layer structure and prevents the semiconductor elements from displacement.

Abstract translation: 公开了一种半导体封装，其包括：具有至少一个开口的载体; 形成在所述载体上和所述开口中的多个导电迹线; 设置在所述开口中并电连接到所述导电迹线的第一半导体元件; 设置在所述开口中的所述第一半导体元件上的第二半导体元件; 以及形成在载体上的再分布层结构和用于电连接导电迹线和第二半导体元件的第二半导体元件。 由于半导体元件被嵌入并因此定位在载体的开口中，所以本发明消除了在形成再分配层结构之前进行模制处理并防止半导体元件移位的需要。

公开(公告)号：US10403567B2

公开(公告)日：2019-09-03

申请号：US15866144

申请日：2018-01-09

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yan-Heng Chen ,  Chun-Tang Lin ,  Mu-Hsuan Chan ,  Chieh-Yuan Chi

IPC: H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00 ,  H01L21/56

Abstract: A method for fabricating an electronic package is provided, which includes the steps of: providing an insulating layer having at least an electronic element embedded therein; forming at least a first via hole on one side of the insulating layer; forming a first conductor in the first via hole of the insulating layer; forming on the insulating layer a first circuit structure electrically connected to the electronic element and the first conductor; and forming a second via hole on the other side of the insulating layer, wherein the second via hole communicates with the first via hole. As such, the second via hole and the first via hole constitute a through hole. Since the through hole is fabricated through two steps, the aspect ratio (depth/width) of the through hole can be adjusted according to the practical need so as to improve the process yield.

公开(公告)号：US20180130727A1

公开(公告)日：2018-05-10

申请号：US15866144

申请日：2018-01-09

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yan-Heng Chen ,  Chun-Tang Lin ,  Mu-Hsuan Chan ,  Chieh-Yuan Chi

IPC: H01L23/498 ,  H01L25/00 ,  H01L23/538 ,  H01L23/00 ,  H01L25/10 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/49811 ,  H01L21/486 ,  H01L21/568 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/18162

Abstract: A method for fabricating an electronic package is provided, which includes the steps of: providing an insulating layer having at least an electronic element embedded therein; forming at least a first via hole on one side of the insulating layer; forming a first conductor in the first via hole of the insulating layer; forming on the insulating layer a first circuit structure electrically connected to the electronic element and the first conductor; and forming a second via hole on the other side of the insulating layer, wherein the second via hole communicates with the first via hole. As such, the second via hole and the first via hole constitute a through hole. Since the through hole is fabricated through two steps, the aspect ratio (depth/width) of the through hole can be adjusted according to the practical need so as to improve the process yield.

公开(公告)号：US09768140B2

公开(公告)日：2017-09-19

申请号：US14515922

申请日：2014-10-16

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yan-Heng Chen ,  Mu-Hsuan Chan ,  Chieh-Yuan Chi

IPC: H01L21/00 ,  H01L23/00 ,  H01L21/56 ,  H01L21/311 ,  H01L23/31

CPC classification number: H01L24/19 ,  H01L21/31144 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L24/20 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2225/1035 ,  H01L2924/37001

Abstract: A method for fabricating a package structure is provided, which includes the steps of: providing an encapsulant encapsulating at least an electronic element; forming a shaping layer on a surface of the encapsulant, wherein the shaping layer has at least an opening exposing a portion of the surface of the encapsulant; forming at least a through hole corresponding in position to the opening and penetrating the encapsulant; and forming a conductor in the through hole. The shaping layer facilitates to prevent deformation of the through hole.

公开(公告)号：US09589841B2

公开(公告)日：2017-03-07

申请号：US14981364

申请日：2015-12-28

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yan-Heng Chen ,  Yi-Feng Chang

IPC: H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L21/78 ,  H01L21/48 ,  H01L23/538

CPC classification number: H01L21/78 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/5389 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/92125 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A method for fabricating an electronic package is provided, including the steps of: providing at least a packaging structure, wherein the packaging structure has a packaging substrate having opposite first and second sides, an electronic element disposed on the first side of the packaging substrate and a plurality of conductors formed on the first side of the packaging substrate; encapsulating the packaging structure with an insulating layer, wherein the insulating layer covers the packaging substrate; and forming an RDL (Redistribution Layer) structure on the insulating layer, wherein the RDL structure is electrically connected to the conductors. Therefore, the area of the insulating layer is not required to correspond to the area of the packaging substrate, thus allowing the area of the packaging substrate to be reduced according to the practical need so as to reduce the width of the electronic package.

Abstract translation: 提供了一种制造电子封装件的方法，包括以下步骤：提供至少一种包装结构，其中该封装结构具有包含相对的第一和第二侧的封装基板，设置在该封装基板的第一面上的电子元件，以及 形成在所述封装基板的第一面上的多个导体; 用绝缘层封装封装结构，其中绝缘层覆盖封装衬底; 以及在所述绝缘层上形成RDL（再分配层）结构，其中所述RDL结构电连接到所述导体。 因此，绝缘层的面积不需要对应于封装基板的面积，因此可以根据实际需要减小封装基板的面积，以减小电子封装的宽度。

公开(公告)号：US20160240466A1

公开(公告)日：2016-08-18

申请号：US14981364

申请日：2015-12-28

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yan-Heng Chen ,  Yi-Feng Chang

IPC: H01L23/498 ,  H01L21/78 ,  H01L21/56 ,  H01L23/31 ,  H01L21/48

CPC classification number: H01L21/78 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/5389 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/92125 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A method for fabricating an electronic package is provided, including the steps of: providing at least a packaging structure, wherein the packaging structure has a packaging substrate having opposite first and second sides, an electronic element disposed on the first side of the packaging substrate and a plurality of conductors formed on the first side of the packaging substrate; encapsulating the packaging structure with an insulating layer, wherein the insulating layer covers the packaging substrate; and forming an RDL (Redistribution Layer) structure on the insulating layer, wherein the RDL structure is electrically connected to the conductors. Therefore, the area of the insulating layer is not required to correspond to the area of the packaging substrate, thus allowing the area of the packaging substrate to be reduced according to the practical need so as to reduce the width of the electronic package.

Abstract translation: 提供了一种制造电子封装件的方法，包括以下步骤：提供至少一种包装结构，其中该封装结构具有包含相对的第一和第二侧的封装基板，设置在该封装基板的第一面上的电子元件，以及 形成在所述封装基板的第一面上的多个导体; 用绝缘层封装封装结构，其中绝缘层覆盖封装衬底; 以及在所述绝缘层上形成RDL（再分配层）结构，其中所述RDL结构电连接到所述导体。 因此，绝缘层的面积不需要对应于封装基板的面积，因此可以根据实际需要减小封装基板的面积，以减小电子封装的宽度。

公开(公告)号：US09397081B2

公开(公告)日：2016-07-19

申请号：US14873445

申请日：2015-10-02

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yan-Heng Chen ,  Chun-Tang Lin ,  Yan-Yi Liao ,  Hung-Wen Liu ,  Chieh-Yuan Chi ,  Hsi-Chang Hsu

IPC: H01L23/31 ,  H01L23/13 ,  H01L23/538 ,  H01L25/065 ,  H01L25/00 ,  H01L21/768

CPC classification number: H01L25/50 ,  H01L21/4846 ,  H01L21/486 ,  H01L21/568 ,  H01L21/768 ,  H01L21/76877 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06558 ,  H01L2924/12042 ,  H01L2924/15156 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/3511 ,  H01L2224/82 ,  H01L2224/83 ,  H01L2924/00

Abstract: A semiconductor package is disclosed, which includes: a carrier having at least an opening; a plurality of conductive traces formed on the carrier and in the opening; a first semiconductor element disposed in the opening and electrically connected to the conductive traces; a second semiconductor element disposed on the first semiconductor element in the opening; and a redistribution layer structure formed on the carrier and the second semiconductor element for electrically connecting the conductive traces and the second semiconductor element. Since the semiconductor elements are embedded and therefore positioned in the opening of the carrier, the present invention eliminates the need to perform a molding process before forming the redistribution layer structure and prevents the semiconductor elements from displacement.

Abstract translation: 公开了一种半导体封装，其包括：具有至少一个开口的载体; 形成在所述载体上和所述开口中的多个导电迹线; 设置在所述开口中并电连接到所述导电迹线的第一半导体元件; 设置在所述开口中的所述第一半导体元件上的第二半导体元件; 以及形成在载体上的再分布层结构和用于电连接导电迹线和第二半导体元件的第二半导体元件。 由于半导体元件被嵌入并因此定位在载体的开口中，所以本发明消除了在形成再分配层结构之前进行模制处理并防止半导体元件移位的需要。

公开(公告)号：US09337061B2

公开(公告)日：2016-05-10

申请号：US14151153

申请日：2014-01-09

Applicant: Siliconware Precision Industries Co., Ltd

Inventor： Yan-Heng Chen ,  Chun-Tang Lin ,  Mu-Hsuan Chan ,  Chieh-Yuan Chi ,  Yan-Yi Liao

IPC: H01L21/00 ,  H01L21/52 ,  H01L21/78 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L21/52 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/12105 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00

Abstract: A fabrication method of a semiconductor package is disclosed, which includes the steps of: providing a carrier; disposing at least a semiconductor element on the carrier; forming an encapsulant on the carrier and the semiconductor element for encapsulating the semiconductor element; removing the carrier; disposing a pressure member on the encapsulant; and forming an RDL structure on the semiconductor element and the encapsulant, thereby suppressing internal stresses through the pressure member so as to mitigate warpage on edges of the encapsulant.

Abstract translation: 公开了一种半导体封装的制造方法，其包括以下步骤：提供载体; 在载体上设置至少一个半导体元件; 在所述载体和所述半导体元件上形成用于封装所述半导体元件的密封剂; 移除载体; 将压力构件设置在密封剂上; 以及在半导体元件和密封剂上形成RDL结构，由此抑制通过压力构件的内部应力，从而减轻密封剂边缘的翘曲。

公开(公告)号：US20160049376A1

公开(公告)日：2016-02-18

申请号：US14515922

申请日：2014-10-16

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yan-Heng Chen ,  Mu-Hsuan Chan ,  Chieh-Yuan Chi

IPC: H01L23/00 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/768

CPC classification number: H01L24/19 ,  H01L21/31144 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L24/20 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2225/1035 ,  H01L2924/37001

Abstract: A method for fabricating a package structure is provided, which includes the steps of: providing an encapsulant encapsulating at least an electronic element; forming a shaping layer on a surface of the encapsulant, wherein the shaping layer has at least an opening exposing a portion of the surface of the encapsulant; forming at least a through hole corresponding in position to the opening and penetrating the encapsulant; and forming a conductor in the through hole. The shaping layer facilitates to prevent deformation of the through hole.

Abstract translation: 提供一种制造封装结构的方法，其包括以下步骤：提供封装至少一个电子元件的密封剂; 在所述密封剂的表面上形成成形层，其中所述成形层具有暴露所述密封剂表面的一部分的至少一个开口; 至少形成对应于所述开口的位置并穿透所述密封剂的通孔; 并在通孔中形成导体。 成形层有助于防止通孔的变形。

公开(公告)号：US09177859B2

公开(公告)日：2015-11-03

申请号：US14013420

申请日：2013-08-29

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yan-Heng Chen ,  Chun-Tang Lin ,  Yan-Yi Liao ,  Hung-Wen Liu ,  Chieh-Yuan Chi ,  Hsi-Chang Hsu

IPC: H01L23/31 ,  H01L23/13 ,  H01L23/538 ,  H01L21/768 ,  H01L23/498 ,  H01L21/48 ,  H01L25/065 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L25/50 ,  H01L21/4846 ,  H01L21/486 ,  H01L21/568 ,  H01L21/768 ,  H01L21/76877 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06558 ,  H01L2924/12042 ,  H01L2924/15156 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/3511 ,  H01L2224/82 ,  H01L2224/83 ,  H01L2924/00

Abstract: A semiconductor package is disclosed, which includes: a carrier having at least an opening; a plurality of conductive traces formed on the carrier and in the opening; a first semiconductor element disposed in the opening and electrically connected to the conductive traces; a second semiconductor element disposed on the first semiconductor element in the opening; and a redistribution layer structure formed on the carrier and the second semiconductor element for electrically connecting the conductive traces and the second semiconductor element. Since the semiconductor elements are embedded and therefore positioned in the opening of the carrier, the present invention eliminates the need to perform a molding process before forming the redistribution layer structure and prevents the semiconductor elements from displacement.

Abstract translation: 公开了一种半导体封装，其包括：具有至少一个开口的载体; 形成在所述载体上和所述开口中的多个导电迹线; 设置在所述开口中并电连接到所述导电迹线的第一半导体元件; 设置在所述开口中的所述第一半导体元件上的第二半导体元件; 以及形成在载体上的再分布层结构和用于电连接导电迹线和第二半导体元件的第二半导体元件。 由于半导体元件被嵌入并因此定位在载体的开口中，所以本发明消除了在形成再分配层结构之前进行模制处理并防止半导体元件移位的需要。