公开(公告)号：US20110284386A1

公开(公告)日：2011-11-24

申请号：US13110488

申请日：2011-05-18

申请人： Mark J. Willey ,  Steven T. Mayer

发明人： Mark J. Willey ,  Steven T. Mayer

IPC分类号： C25D5/02 ,  C25D19/00 ,  C25D3/38

CPC分类号： C25D3/38 ,  C25D5/022 ,  C25D7/123 ,  C25D21/12 ,  H01L21/2885 ,  H01L21/76879 ,  H01L21/76898 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for electrofilling large, high aspect ratio recessed features with copper without depositing substantial amounts of copper in the field region is provided. The method allows completely filling recessed features having aspect ratios of at least about 5:1 such as at least about 10:1, and widths of at least about 1 μm in a substantially void-free manner without depositing more than 5% of copper in the field region (relative to the thickness deposited in the recessed feature). The method involves contacting the substrate having one or more large, high aspect ratio recessed features (such as a TSVs) with an electrolyte comprising copper ions and an organic dual state inhibitor (DSI) configured for inhibiting copper deposition in the field region, and electrodepositing copper under potential-controlled conditions, where the potential is controlled not exceed the critical potential of the DSI.

摘要翻译： 提供了一种用于电镀大量，高纵横比的凹陷特征与铜而不在现场区域中沉积大量铜的方法。 该方法允许以基本无空隙的方式完全填充具有至少约5:1的纵横比（例如至少约10:1）和至少约1μm的宽度的凹陷特征，而不沉积超过5％的铜 场区域（相对于沉积在凹陷特征中的厚度）。 该方法包括将具有一个或多个大的，高纵横比的凹陷特征（例如TSV）的基底与包含铜离子的电解质和被配置用于抑制场区中的铜沉积的有机双态抑制剂（DSI）接触，以及电沉积 在电势控制条件下，电位控制的铜不超过DSI的临界电位。

公开(公告)号：US08026174B1

公开(公告)日：2011-09-27

申请号：US12496120

申请日：2009-07-01

申请人： Evan E. Patton ,  Theodore Cacouris ,  Eliot Broadbent ,  Steven T. Mayer

发明人： Evan E. Patton ,  Theodore Cacouris ,  Eliot Broadbent ,  Steven T. Mayer

IPC分类号： H01L21/445 ,  C25D17/28

CPC分类号： C25D17/001 ,  C25D3/38 ,  C25D5/10 ,  H01L21/2885 ,  H01L21/67161 ,  H01L21/6719 ,  H01L21/6723 ,  H01L21/67751 ,  H01L21/76877 ,  Y10T29/41

摘要： Methods and apparatus are provided for processing semiconductor wafers sequentially. Sequential processes employ multi-station processing modules, where particular encompassing wafer processes are divided into sub-processes, each optimized for increasing wafer to wafer uniformity, result quality, and overall wafer throughput. In one example, a copper electroplating module includes separate stations for wetting, initiation, seed layer repair, fill, overburden, reclaim, and rinse.

摘要翻译： 提供了顺序处理半导体晶片的方法和装置。 顺序过程采用多工位处理模块，其中特别包含的晶片工艺被分为子工艺，每个子工艺被优化用于增加晶圆到晶片的均匀性，结果质量和整个晶片生产量。 在一个示例中，铜电镀模块包括用于润湿，起始，种子层修复，填充，覆盖层，回收和冲洗的分离站。

公开(公告)号：US20090277801A1

公开(公告)日：2009-11-12

申请号：US11890541

申请日：2007-08-06

申请人： Steven T. Mayer ,  John Stephen Drewery ,  Eric G. Webb

发明人： Steven T. Mayer ,  John Stephen Drewery ,  Eric G. Webb

IPC分类号： B23H3/00 ,  B05D3/00 ,  C25B9/00

CPC分类号： C25D5/022 ,  C25F5/00 ,  H05K3/07 ,  H05K3/108 ,  H05K2203/0108 ,  H05K2203/0392 ,  H05K2203/0537 ,  H05K2203/0713

摘要： Selectively accelerated or selectively inhibited metal deposition is performed to form metal structures of an electronic device. A desired pattern of an accelerator or of an inhibitor is applied to the substrate; for example, by stamping the substrate with a patterned stamp or spraying a solution using an inkjet printer. In other embodiments, a global layer of accelerator or inhibitor is applied to a substrate and selectively modified in a desired pattern. Thereafter, selective metal deposition is performed.

摘要翻译： 进行选择性加速或选择性抑制金属沉积以形成电子器件的金属结构。 将所需的促进剂或抑制剂的图案施加到基材上; 例如，通过用图案化的印模冲压基板或使用喷墨打印机喷涂溶液。 在其它实施方案中，将全局加速剂或抑制剂层施加到基底上并以期望的图案选择性地修饰。 此后，进行选择性金属沉积。

公开(公告)号：US07531079B1

公开(公告)日：2009-05-12

申请号：US11065708

申请日：2005-02-23

申请人： Steven T. Mayer ,  John S. Drewery

发明人： Steven T. Mayer ,  John S. Drewery

IPC分类号： C25F3/16

CPC分类号： B23H5/08 ,  C25F3/16 ,  H01L21/32125 ,  H01L21/7684

摘要： The present invention pertains to apparatus and methods for planarization of metal surfaces having both recessed and raised features, over a large range of feature sizes. The invention accomplishes this by increasing the fluid agitation in raised regions with respect to recessed regions. That is, the agitation of the electropolishing bath fluid is agitated or exchanged as a function of elevation on the metal film profile. The higher the elevation, the greater the movement or exchange rate of bath fluid. In preferred methods of the invention, this agitation is achieved through the use of a microporous electropolishing pad that moves over (either near or in contact with) the surface of the wafer during the electropolishing process. Thus, methods of the invention are electropolishing methods, which in some cases include mechanical polishing elements.

摘要翻译： 本发明涉及在大范围的特征尺寸上具有凹陷和凸起特征的金属表面的平坦化的装置和方法。 本发明通过增加相对于凹陷区域的凸起区域中的流体搅拌来实现。 也就是说，作为金属膜轮廓上的仰角的函数来搅动或更换电抛光浴液的搅动。 海拔越高，浴液的运动或汇率越高。 在本发明的优选方法中，通过使用在电解抛光过程中在晶片表面上移动（接近或接触）的微孔电解抛光垫来实现该搅拌。 因此，本发明的方法是电抛光方法，其在一些情况下包括机械抛光元件。

公开(公告)号：US07405163B1

公开(公告)日：2008-07-29

申请号：US10824069

申请日：2004-04-13

申请人： John Stephen Drewery ,  Steven T. Mayer

发明人： John Stephen Drewery ,  Steven T. Mayer

IPC分类号： H01L21/303

CPC分类号： H05K3/184 ,  H01L21/4846 ,  H05K3/045 ,  H05K3/107 ,  H05K2203/054 ,  H05K2203/072

摘要： An accelerator solution is globally applied to a workpiece to form an accelerator film, and then a portion of the accelerator film is selectively removed from the workpiece to form an acceleration region having a higher concentration of accelerator. The higher concentration of accelerator causes metal to deposit at a faster rate in the acceleration region than in a non-accelerated region for the duration of metal deposition. To make a metal feature, a resist layer is applied to a workpiece surface and patterned to form a recessed region and a field region. Then, a metal seed layer is deposited on the workpiece surface. An accelerator solution is applied so that an accelerator film forms on the metal seed layer. A portion of the accelerator film is selectively removed from the field region, leaving another portion of the accelerator film in the recessed region. Then, copper is electroplated onto the workpiece, and the copper plates at an accelerated rate in the recessed region, resulting in a greater thickness of copper in the recessed region compared to copper in the field region. A wet etch is performed to remove copper from the field region. Then, the resist is removed from the field region, resulting in a coarse copper wire.

摘要翻译： 将加速器溶液全局应用于工件以形成加速剂膜，然后将一部分加速剂膜从工件中选择性地除去，形成加速剂浓度较高的加速区域。 在金属沉积期间，较高浓度的促进剂会导致金属在加速区域以比非加速区域更快的速率沉积。 为了形成金属特征，将抗蚀剂层施加到工件表面并图案化以形成凹陷区域和场区域。 然后，金属种子层沉积在工件表面上。 施加促进剂溶液，使得在金属种子层上形成促进剂膜。 加速膜的一部分从场区域选择性地去除，另外部分加速器膜在凹陷区域中。 然后，在凹陷区域中以铜加速的方式将铜电镀到工件上，铜板以加速的速度电镀，导致与凹陷区域中的铜相比，凹陷区域中的铜的厚度更大。 执行湿蚀刻以从场区域去除铜。 然后，从场区域去除抗蚀剂，导致粗铜线。

公开(公告)号：US06946065B1

公开(公告)日：2005-09-20

申请号：US09716016

申请日：2000-11-16

申请人： Steven T. Mayer ,  Vijay Bhaskaran ,  Evan E. Patton ,  Robert L. Jackson ,  Jonathan Reid

发明人： Steven T. Mayer ,  Vijay Bhaskaran ,  Evan E. Patton ,  Robert L. Jackson ,  Jonathan Reid

IPC分类号： C25D3/38 ,  C25D5/18 ,  H05K3/42 ,  H01L21/768

CPC分类号： C25D3/02 ,  C25D3/38 ,  C25D5/022 ,  C25D5/18 ,  H01L21/2885 ,  H01L21/76877 ,  H05K3/423

摘要： Several techniques are described for reducing or mitigating the formation of seams and/or voids in electroplating the interior regions of microscopic recessed features. Cathodic polarization is used to mitigate the deleterious effects of introducing a substrate plated with a seed layer into an electroplating solution. Also described are diffusion-controlled electroplating techniques to provide for bottom-up filling of trenches and vias, avoiding thereby sidewalls growing together to create seams/voids. A preliminary plating step is also described that plates a thin film of conductor on the interior surfaces of features leading to adequate electrical conductivity to the feature bottom, facilitating bottom-up filling.

摘要翻译： 描述了几种用于减少或减轻在电镀微观凹陷特征的内部区域中的接缝和/或空隙的形成的技术。 阴极极化用于减轻将电镀有种子层的基板引入电镀溶液中的有害影响。 还描述了扩散控制的电镀技术，以提供沟槽和通孔的自下而上的填充，从而避免由此侧壁一起生长以产生接缝/空隙。 还描述了初步电镀步骤，在特征的内表面上镀覆导电薄膜，导致特征底部具有足够的导电性，便于自底向上填充。

公开(公告)号：US06709565B2

公开(公告)日：2004-03-23

申请号：US09967075

申请日：2001-09-28

申请人： Steven T. Mayer ,  Robert J. Contolini ,  Eliot K. Broadbent ,  John S. Drewery

发明人： Steven T. Mayer ,  Robert J. Contolini ,  Eliot K. Broadbent ,  John S. Drewery

IPC分类号： B23H1100

CPC分类号： B23H5/08 ,  H01L21/32115 ,  H01L21/3212 ,  H01L21/32134

摘要： The present invention pertains to apparatus and methods for planarization of metal surfaces having both recessed and raised features, over a large range of feature sizes. The invention accomplishes this by increasing the fluid agitation in raised regions with respect to recessed regions. That is, the agitation of the electropolishing bath fluid is agitated or exchanged as a function of elevation on the metal film profile. The higher the elevation, the greater the movement or exchange rate of bath fluid. In preferred methods of the invention, this agitation is achieved through the use of a microporous electropolishing pad that moves over (either near or in contact with) the surface of the wafer during the electropolishing process. Thus, methods of the invention are electropolishing methods, which in some cases include mechanical polishing elements.

摘要翻译： 本发明涉及在大范围的特征尺寸上具有凹陷和凸起特征的金属表面的平坦化的装置和方法。 本发明通过增加相对于凹陷区域的凸起区域中的流体搅拌来实现。 也就是说，作为金属膜轮廓上的仰角的函数来搅动或更换电抛光浴液的搅动。 海拔越高，浴液的运动或汇率越高。 在本发明的优选方法中，通过使用在电解抛光过程中在晶片表面上移动（接近或接触）的微孔电解抛光垫来实现该搅拌。 因此，本发明的方法是电抛光方法，其在一些情况下包括机械抛光元件。

公开(公告)号：US06402923B1

公开(公告)日：2002-06-11

申请号：US09537467

申请日：2000-03-27

申请人： Steven T. Mayer ,  Richard Hill ,  Alain Harrus ,  Evan Patton ,  Robert Contolini ,  Steve Taatjes ,  Jon Reid

发明人： Steven T. Mayer ,  Richard Hill ,  Alain Harrus ,  Evan Patton ,  Robert Contolini ,  Steve Taatjes ,  Jon Reid

IPC分类号： C25D500

CPC分类号： C25D17/08 ,  C25D7/123 ,  C25D17/001 ,  C25D17/008 ,  C25D17/12 ,  Y10S204/07

摘要： An electrochemical reactor is used to electrofill damascene architecture for integrated circuits. A shield is used to screen the applied field during electroplating operations to compensate for potential drop along the radius of a wafer. The shield establishes an inverse potential drop in the electrolytic fluid to overcome the resistance of a thin film seed layer of copper on the wafer.

摘要翻译： 电化学反应器用于集成电路的大马士革结构。 在电镀操作期间使用屏蔽来屏蔽施加的场，以补偿沿着晶片半径的电位降。 屏蔽层在电解液中建立反向电位降，以克服晶片上铜的薄膜晶种层的电阻。

公开(公告)号：US06379842B1

公开(公告)日：2002-04-30

申请号：US09413744

申请日：1999-10-06

申请人： Steven T. Mayer

发明人： Steven T. Mayer

IPC分类号： H01M458

CPC分类号： H01M4/525 ,  H01M4/131 ,  H01M4/133 ,  H01M4/505 ,  H01M10/0525

摘要： Positive electrodes including a lithium nickel cobalt metal oxide are disclosed. The lithium nickel cobalt metal oxides have the general formula LixNiyCOzMnO2, where M is selected from the group consisting of aluminum, titanium, tungsten, chromium, molybdenum, magnesium, tantalum, silicon, and combinations thereof, x is between about 0 and about 1 and can be varied within this range by electrochemical insertion and extraction, the sum of y+z+n is about 1, n ranges between above 0 to about 0.25, y and z are both greater than 0, and the ratio z/y ranges from above 0 to about 1/3. Also disclosed are composite positive electrodes including the above-described lithium nickel cobalt metal oxides together with a lithium manganese metal oxide of the formula LixMn2−rM1rO4, where r is a value between 0 and 1 and M1 is chromium, titanium, tungsten, nickel, cobalt, iron, tin, zinc, zirconium, silicon, or a combination thereof.

摘要翻译： 公开了包括锂镍钴金属氧化物的正电极。 锂镍钴金属氧化物具有通式LixNiyCOzMnO2，其中M选自铝，钛，钨，铬，钼，镁，钽，硅及其组合，x为约0至约1，以及 可以在该范围内通过电化学插入和提取而变化，y + z + n的和为约1，n在0至约0.25之间，y和z都大于0，z / y的比率范围为 高于0至约1/3。 还公开了包括上述锂镍钴金属氧化物和式LixMn2-rM1rO4的锂锰金属氧化物的复合正电极，其中r是0和1之间的值，M1是铬，钛，钨，镍， 钴，铁，锡，锌，锆，硅或其组合。

公开(公告)号：US06201924B1

公开(公告)日：2001-03-13

申请号：US08482905

申请日：1995-06-07

申请人： Stephen E. Crane ,  LeeAnn Heringer ,  Michael Shinsky ,  Gerald A. Raitzer ,  Michael A. Ogrinc ,  Steven T. Mayer

发明人： Stephen E. Crane ,  LeeAnn Heringer ,  Michael Shinsky ,  Gerald A. Raitzer ,  Michael A. Ogrinc ,  Steven T. Mayer

IPC分类号： H04N576

CPC分类号： G11B27/024 ,  G11B27/028 ,  G11B27/032 ,  G11B27/034 ,  G11B27/34 ,  G11B2220/20 ,  G11B2220/2525 ,  G11B2220/90

摘要： A disk-assisted system for editing video tapes. Source material from video tapes is logged onto random access storage such as a hard disk drive using of a Macintosh-based computer system. At any one time, only a small portion of the tape material is stored as video frames on the computer disk. By software control, material is cached back and forth between the computer disk and the video tape. Thus editing is accomplished and an edit decision list constructed for compilation of the final video production. This provides the advantage of fast access time for editing of the material which is on the disk while allowing actual physical editing at the end of the project of the actual video tape material. The processes of logging the material onto the disk and editing the final tape are performed automatically.

摘要翻译： 用于编辑录像带的磁盘辅助系统。 来自视频磁带的源材料被记录到使用基于Macintosh的计算机系统的随机存取存储器例如硬盘驱动器上。 在任何一个时间，只有一小部分磁带材料作为视频帧存储在计算机磁盘上。 通过软件控制，材料在计算机磁盘和录像带之间来回缓存。 因此编辑完成并且为编译最终的视频制作而构造的编辑决定列表。 这提供了用于编辑磁盘上的材料的快速访问时间的优点，同时允许在实际录像带材料的项目结束时的实际物理编辑。 将材料记录到磁盘上并编辑最终磁带的过程自动执行。