公开(公告)号：US6162586A

公开(公告)日：2000-12-19

申请号：US73734

申请日：1998-05-06

Applicant: Samit S. Sengupta ,  Daniel C. Baker ,  Subhas Bothra

Inventor： Samit S. Sengupta ,  Daniel C. Baker ,  Subhas Bothra

IPC: G03F7/09 ,  H01L21/3213 ,  G03C5/00

CPC classification number: G03F7/091 ,  H01L21/32139

Abstract: Disclosed is a method for making a metallization layered stack over an oxide layer of a semiconductor substrate, and a metallization layered stack that assists in providing superior deep UV photolithography resolution. The method includes forming a bottom titanium nitride layer over the oxide layer, and forming an aluminum metallization layer over the bottom titanium nitride layer. The method further includes forming a top titanium nitride layer over the aluminum metallization layer, such that the forming of the top titanium nitride layer includes: (a) placing the semiconductor substrate in an ionized metal plasma chamber having an RF powered coil and a titanium target; (b) introducing an argon gas and a nitrogen gas into the ionized metal plasma chamber; (c) pressuring up the ionized metal plasma chamber to a pressure of between about 10 mTorr and about 50 mTorr, whereby the top titanium nitride layer is formed as a dense titanium nitride film.

Abstract translation: 公开了一种用于在半导体衬底的氧化物层上形成金属化层叠叠层的方法，以及有助于提供优异的深紫外光刻分辨率的金属化层叠叠层。 该方法包括在氧化物层上形成底部氮化钛层，并在底部氮化钛层上形成铝金属化层。 该方法还包括在铝金属化层上形成顶部氮化钛层，使得顶部氮化钛层的形成包括：（a）将半导体衬底放置在具有RF供电线圈和钛靶的电离金属等离子体室中 ; （b）将氩气和氮气引入离子化金属等离子体室中; （c）将离子化金属等离子体室加压到约10mTorr至约50mTorr之间的压力，由此顶部氮化钛层形成为致密的氮化钛膜。

公开(公告)号：US6156626A

公开(公告)日：2000-12-05

申请号：US259744

申请日：1999-02-27

Applicant: Subhas Bothra

Inventor： Subhas Bothra

IPC: H01L21/60 ,  H01L21/479 ,  H01L21/326 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC classification number: H01L24/05 ,  H01L24/81 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05094 ,  H01L2224/05095 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/48463 ,  H01L2224/81801 ,  H01L2224/85424 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2224/9202 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/14

Abstract: A process and system for connecting a semiconductor chip to a substrate is provided. The process includes providing the substrate that is configured to receive the semiconductor chip that has a bonding pad. The substrate has a first side that is suited to be connected to the semiconductor chip and a second side that is opposite the first side. The process then includes designing a metallization bonding structure on the first side of the substrate. The metallization bonding structure has a first end, a second end, and a bend defined between the first end and the second end. Then, an oxide passivation layer is defined over the first side that includes the metallization bonding structure. A bonding via is then defined through the passivation layer. The bonding via is configured to be aligned with the bend of the metallization bonding structure. The semiconductor chip is then joined to the oxide passivation layer, such that the bonding pad is aligned with the bonding via and the bend of the metallization bonding structure. The process further includes the application of a current between the first end and the second end of the metallization bonding structure. The applied current is configured to cause a flow of electrons in an opposite direction of the current and a flow of metallization atoms in the metallization bonding structure toward the bend and into the bonding via. A reliable conductive bond between the substrate and the bonding pad of the semiconductor chip is thus established without the need for wire bonds or solder bumps.

Abstract translation: 提供了一种用于将半导体芯片连接到基板的工艺和系统。 该方法包括提供被配置为接收具有接合焊盘的半导体芯片的衬底。 衬底具有适于连接到半导体芯片的第一侧和与第一侧相对的第二侧。 该方法然后包括在衬底的第一侧上设计金属化接合结构。 金属化接合结构具有第一端部，第二端部和限定在第一端部和第二端部之间的弯曲部。 然后，在包括金属化接合结构的第一侧上限定氧化物钝化层。 然后通过钝化层限定结合通孔。 结合通孔被配置为与金属化接合结构的弯曲部对准。 然后将半导体芯片接合到氧化物钝化层，使得焊盘与焊接通孔和金属化接合结构的弯曲部对准。 该方法还包括在金属化接合结构的第一端和第二端之间施加电流。 施加的电流被配置为使电子沿电流的相反方向流动，并且金属化接合结构中的金属化原子的流动朝向弯曲并进入结合通孔。 因此，在不需要引线键合或焊料凸块的情况下，建立了衬底和半导体芯片的焊盘之间的可靠的导电结合。

公开(公告)号：US6143642A

公开(公告)日：2000-11-07

申请号：US995650

申请日：1997-12-22

Applicant: Harlan Lee Sur, Jr. ,  Subhas Bothra

Inventor： Harlan Lee Sur, Jr. ,  Subhas Bothra

IPC: H01L21/768 ,  H01L23/525 ,  H01L27/10 ,  H01L21/4763

CPC classification number: H01L27/10 ,  H01L21/76888 ,  H01L23/525 ,  H01L2924/0002

Abstract: Disclosed is a method for making a programmable structure on a semiconductor substrate. The semiconductor structure has a first dielectric layer. The method includes plasma patterning a first metallization layer over the first dielectric layer. Forming a second dielectric layer over the first metallization layer and the first dielectric layer. Forming a plurality of tungsten plugs in the second dielectric layer. Each of the plurality of tungsten plugs are in electrical contact with the first metallization layer. Plasma patterning a second metallization layer over the second dielectric layer and the plurality of tungsten plugs, such that at least a gap over each of the tungsten plugs is not covered by the second metallization layer. Applying a programming electron dose to a portion of the second metallization layer. The method further includes submersing the semiconductor substrate into a basic solution to remove each of the plurality of tungsten plugs except for a tungsten plug that is in electrical contact with the portion of the second metallization layer that received the applied programming electron dose.

Abstract translation: 公开了一种在半导体衬底上制造可编程结构的方法。 半导体结构具有第一电介质层。 该方法包括在第一介电层上的等离子体图案化第一金属化层。 在第一金属化层和第一介电层上形成第二电介质层。 在第二电介质层中形成多个钨塞。 多个钨插塞中的每一个与第一金属化层电接触。 等离子体在第二电介质层和多个钨插塞上图案化第二金属化层，使得每个钨插塞上的至少间隙不被第二金属化层覆盖。 对第二金属化层的一部分施加编程电子剂量。 该方法还包括将半导体衬底浸入基本溶液中以除去除了接收施加的编程电子剂量的与第二金属化层的部分电接触的钨插塞之外的多个钨插塞中的每一个。

公开(公告)号：US6129613A

公开(公告)日：2000-10-10

申请号：US16152

申请日：1998-01-30

Applicant: Subhas Bothra

Inventor： Subhas Bothra

IPC: B24B37/30 ,  B24B49/10 ,  B24B49/16 ,  G01L1/14 ,  G01L5/00 ,  B24B7/00 ,  B24B9/00 ,  H01L29/82

CPC classification number: B24B37/30 ,  B24B49/10 ,  B24B49/16 ,  G01L1/148 ,  G01L5/008

Abstract: A pressure sensing structure for measuring a local pressure on a surface of a wafer and a wafer carrier for communicating with the wafer is disclosed. The pressure sensing structure includes a conductive via extending through the wafer, a pressure transducer electrically connected to a first side of the conductive via, and a connector arranged in electrical contact with a second side of the conductive via. Further, a wafer incorporating multiple such pressure sensing structures is disclosed. In addition, a pressure sensing structure further including integrated circuitry in electrical contact with the pressure transducer and a conductive via is disclosed. The pressure sensing structure is well suited for use in sensing pressure variations throughout the surface of the wafer when a selected wafer layer is undergoing a chemical mechanical polishing operation.

Abstract translation: 公开了一种用于测量晶片表面上的局部压力和用于与晶片通信的晶片载体的压力感测结构。 压力感测结构包括延伸穿过晶片的导电通孔，电连接到导电通孔的第一侧的压力传感器，以及布置成与导电通孔的第二侧电接触的连接器。 此外，公开了并入了多个这样的压力感测结构的晶片。 此外，公开了还包括与压力传感器电连接的集成电路和导电通孔的压力感测结构。 当所选择的晶片层经历化学机械抛光操作时，压力感测结构非常适合用于感测晶片整个表面上的压力变化。

公开(公告)号：US6077762A

公开(公告)日：2000-06-20

申请号：US995652

申请日：1997-12-22

Applicant: Victor C. Liang ,  Subhas Bothra ,  Harlan Lee Sur, Jr.

Inventor： Victor C. Liang ,  Subhas Bothra ,  Harlan Lee Sur, Jr.

IPC: H01L21/02 ,  H01L21/306 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/3205

CPC classification number: H01L21/02071 ,  H01L21/76838 ,  H01L21/02052 ,  H01L21/32136 ,  Y10S438/906 ,  Y10S438/972

Abstract: Disclosed is a method for making reliable interconnect structures on a semiconductor substrate having a first dielectric layer. The method includes plasma patterning a first metallization layer that lies over the first dielectric layer. Forming a second dielectric layer over the first metallization layer and the first dielectric layer. Forming a plurality of tungsten plugs in the second dielectric layer, such that each of the plurality of tungsten plugs are in electrical contact with the first metallization layer. Plasma patterning a second metallization layer over the second dielectric layer and the plurality of tungsten plugs, such that at least a gap over at least one of the tungsten plugs is not covered by the second metallization layer and a positive charge is built-up on at least part of the second metallization layer. The method further includes contacting the second metallization layer with a conductive liquid that is electrically grounded. In this manner, the positive charge that is built-up on the at least part of the second metallization layer is neutralized to prevent tungsten plug erosion.

Abstract translation: 公开了一种在具有第一介电层的半导体衬底上制造可靠的互连结构的方法。 该方法包括等离子体图案化位于第一介电层之上的第一金属化层。 在第一金属化层和第一介电层上形成第二电介质层。 在第二电介质层中形成多个钨塞，使得多个钨塞中的每一个与第一金属化层电接触。 等离子体在第二电介质层和多个钨插塞上构图第二金属化层，使得至少一个钨插塞上的至少一个间隙不被第二金属化层覆盖，并且正电荷在 第二金属化层的最少部分。 该方法还包括使第二金属化层与电接地的导电液接触。 以这种方式，积聚在第二金属化层的至少一部分上的正电荷被中和以防止钨插塞侵蚀。

公开(公告)号：US6013927A

公开(公告)日：2000-01-11

申请号：US52859

申请日：1998-03-31

Applicant: Subhas Bothra ,  Harlan Lee Sur, Jr.

Inventor： Subhas Bothra ,  Harlan Lee Sur, Jr.

IPC: H01L21/285 ,  H01L21/3065 ,  H01L21/762 ,  H01L21/763 ,  H01L27/08 ,  H01L29/861 ,  H01L29/76

CPC classification number: H01L21/28525 ,  H01L21/76224 ,  H01L21/763 ,  H01L27/0814 ,  H01L29/861 ,  H01L21/3065

Abstract: Disclosed is a semiconductor diode structure, and method for making semiconductor diode structures for suppressing transistor gate oxide plasma charging damage. The semiconductor diode structure includes a shallow trench isolation region that is configured to isolate an active region of a semiconductor substrate. A doped polysilicon electrode having a first end and a second end. The doped polysilicon electrode is defined in the shallow trench isolation region and the first end is configured to be in electrical contact with the semiconductor substrate. The diode structure further includes a polysilicon gate that has an underlying gate oxide. The polysilicon gate is defined over the active region and extends over part of the shallow trench isolation region so as to make electrical interconnection between the polysilicon gate and the second end of the doped polysilicon electrode.

Abstract translation: 公开了半导体二极管结构以及用于制造用于抑制晶体管栅极氧化物等离子体充电损坏的半导体二极管结构的方法。 半导体二极管结构包括被配置为隔离半导体衬底的有源区的浅沟槽隔离区。 一种具有第一端和第二端的掺杂多晶硅电极。 掺杂多晶硅电极限定在浅沟槽隔离区域中，并且第一端被配置为与半导体衬底电接触。 二极管结构还包括具有底层栅极氧化物的多晶硅栅极。 多晶硅栅极被限定在有源区上并且在浅沟槽隔离区的一部分上延伸，以便在多晶硅栅极和掺杂多晶硅电极的第二端之间形成电互连。

公开(公告)号：US5981378A

公开(公告)日：1999-11-09

申请号：US900501

申请日：1997-07-25

Applicant: Subhas Bothra

Inventor： Subhas Bothra

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/4763

CPC classification number: H01L21/76876 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53223 ,  H01L2924/0002 ,  Y10S438/927

Abstract: Disclosed is an aluminum filled via hole for use in a semiconductor interconnect structure. The aluminum filled via hole of the semiconductor interconnect structure includes a first patterned metallization layer lying over a first dielectric layer. A second dielectric layer overlying the first patterned metallization layer and the first dielectric layer. An aluminum filled via hole defined through the second dielectric layer and in contact with the first patterned metallization layer. The aluminum filled via hole has an electromigration barrier cap over a topmost portion of the aluminum filled via hole that is substantially level with the second dielectric layer. The electromigration barrier cap having a thickness of between about 500 angstroms and about 2,500 angstroms.

Abstract translation: 公开了一种用于半导体互连结构的铝填充通孔。 半导体互连结构的铝填充通孔包括位于第一介电层上的第一图案化金属化层。 覆盖第一图案化金属化层和第一介电层的第二电介质层。 通过第二介电层限定并与第一图案化金属化层接触的铝填充通孔。 铝填充的通孔在铝填充的通孔的最上部具有与第二介电层基本平齐的电迁移阻挡帽。 电迁移阻挡盖的厚度介于约500埃至约2500埃之间。

公开(公告)号：US5915203A

公开(公告)日：1999-06-22

申请号：US872562

申请日：1997-06-10

Applicant: Samit Sengupta ,  Subhas Bothra

Inventor： Samit Sengupta ,  Subhas Bothra

IPC: H01L21/768 ,  H01L23/522 ,  H01L21/44

CPC classification number: H01L23/5226 ,  H01L21/76819 ,  H01L21/76885 ,  H01L2924/0002

Abstract: A method of producing deep submicron vias is described in which a metal blanket layer is formed on a premetal dielectric and patterned to form line elements. An intermetal dielectric is then deposited over the patterned metal and chemically mechanically polished down to the top of the line elements. A second metal blanket layer is then deposited and patterned to form via studs. An intermetal dielectric is also deposited over the patterned metal via studs and polished down to the tops of the studs. The process is repeated until a multilevel integrated circuit is formed.

Abstract translation: 描述了生产深亚微米通孔的方法，其中金属覆盖层形成在金属前电介质上并被图案化以形成线元件。 然后将金属间电介质沉积在图案化的金属上，并化学机械地抛光到线元件的顶部。 然后沉积和图案化第二金属覆盖层以形成通孔螺柱。 金属间电介质也通过螺柱沉积在图案化的金属上，并被抛光到螺柱的顶部。 重复该过程，直到形成多层集成电路。

公开(公告)号：US5882997A

公开(公告)日：1999-03-16

申请号：US955030

申请日：1997-10-21

Applicant: Harlan Lee Sur, Jr. ,  Subhas Bothra

Inventor： Harlan Lee Sur, Jr. ,  Subhas Bothra

IPC: G11C11/412 ,  H01L21/02 ,  H01L27/11 ,  H01L21/44

CPC classification number: H01L28/20 ,  G11C11/412 ,  H01L27/1112

Abstract: A resistive load structure and method for making a resistive load structure for an integrated circuit includes the use of an amorphous silicon "antifuse" material. The resistive load structure can be used in an SRAM cell to provide a load to counteract charge leakage at the drains of two pull-down transistors and two pass transistors of the SRAM cell. The resistive load structure is advantageously formed by depositing an amorphous silicon pad over a conductive via, and the resistance of the resistive load structure is controlled by adjusting the thickness of the amorphous silicon pad and varying the diameter of the underlying conductive via.

Abstract translation: 用于制造用于集成电路的电阻负载结构的电阻负载结构和方法包括使用非晶硅“反熔丝”材料。 电阻负载结构可用于SRAM单元中，以提供负载以抵消SRAM单元的两个下拉晶体管和两个通过晶体管的漏极处的电荷泄漏。 有利地通过在导电通孔上沉积非晶硅垫来形成电阻负载结构，并且通过调节非晶硅垫的厚度并改变下面的导电通孔的直径来控制电阻负载结构的电阻。

公开(公告)号：US5877562A

公开(公告)日：1999-03-02

申请号：US925040

申请日：1997-09-08

Applicant: Harlan Sur ,  Subhas Bothra

Inventor： Harlan Sur ,  Subhas Bothra

IPC: G03F9/00 ,  H01L23/544 ,  H01L23/58

CPC classification number: G03F9/708 ,  G03F9/70 ,  G03F9/7084 ,  H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002

Abstract: A photo alignment structure integral with a substrate enables the alignment apparatus to receive a reflected light signature of the surface topography of the alignment structure. As the circuit is constructed, the alignment target may be built in tandem with the process. The alignment structure is constructed so that its surface will retain sufficient topography to enable the alignment apparatus to properly align.

Abstract translation: 与基板一体的光取向结构使得对准装置能够接收对准结构的表面形貌的反射光标记。 当构建电路时，可以与该过程一起构建对准目标。 对准结构被构造成使得其表面将保持足够的形貌以使对准装置能够正确对准。