公开(公告)号：US20230363180A1

公开(公告)日：2023-11-09

申请号：US18353290

申请日：2023-07-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Katherine H. Chiang ,  Chung-Te Lin ,  Mauricio Manfrini

IPC: H10B61/00 ,  G11C11/16 ,  H10N50/01 ,  H10N50/80

CPC classification number: H10B61/10 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/1657 ,  H10N50/01 ,  H10N50/80

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a magnetic tunnel junction (MTJ) disposed on a first electrode within a dielectric structure over a substrate. A first unipolar selector is disposed within the dielectric structure and is electrically coupled to the first electrode. A second unipolar selector is disposed within the dielectric structure and is electrically coupled to the first electrode. The first unipolar selector laterally extends between a first vertical line intersecting the MTJ and the substrate and a second vertical line intersecting the second unipolar selector and the substrate.

公开(公告)号：US20230363171A1

公开(公告)日：2023-11-09

申请号：US18353954

申请日：2023-07-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Sheng-Chih Lai ,  Chung-Te Lin

IPC: H10B51/20 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66 ,  H10B51/30 ,  H10B51/40

CPC classification number: H10B51/20 ,  H01L29/78391 ,  H01L29/40111 ,  H01L29/66666 ,  H01L29/6684 ,  H01L29/7827 ,  H10B51/30 ,  H10B51/40

Abstract: Various embodiments of the present disclosure are directed towards a metal-ferroelectric-insulator-semiconductor (MFIS) memory device, as well as a method for forming the MFIS memory device. According to some embodiments of the MFIS memory device, a lower source/drain region and an upper source/drain region are vertically stacked. A semiconductor channel overlies the lower source/drain region and underlies the upper source/drain region. The semiconductor channel extends from the lower source/drain region to the upper source/drain region. A control gate electrode extends along a sidewall of the semiconductor channel and further along individual sidewalls of the lower and upper source/drain regions. A gate dielectric layer and a ferroelectric layer separate the control gate electrode from the semiconductor channel and the lower and upper source/drain regions.

公开(公告)号：US20230345732A1

公开(公告)日：2023-10-26

申请号：US18346278

申请日：2023-07-03

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Meng-Han Lin ,  Han-Jong Chia ,  Yi-Ching Liu ,  Chia-En Huang ,  Sheng-Chen Wang ,  Feng-Cheng Yang ,  Chung-Te Lin

IPC: H10B51/20 ,  G11C7/18 ,  G11C8/14 ,  H01L23/522 ,  H10B51/10 ,  H10B51/30

CPC classification number: H10B51/20 ,  G11C7/18 ,  G11C8/14 ,  H01L23/5226 ,  H10B51/10 ,  H10B51/30

Abstract: A memory device, a semiconductor device and manufacturing methods for forming the memory device and the semiconductor device are provided. The memory device includes a stacking structure, a switching layer, channel layers and pairs of conductive pillars. The stacking structure includes alternately stacked isolation layers and word lines, and extends along a first direction. The stacking structure has a staircase portion and a connection portion at an edge region of the stacking structure. The connection portion extends along the staircase portion and located aside the staircase portion, and may not be shaped into a staircase structure. The switching layer covers a sidewall of the stacking structure. The channel layers cover a sidewall of the switching layer, and are laterally spaced apart from one another along the first direction. The pairs of conductive pillars stand on the substrate, and in lateral contact with the switching layer through the channel layers.

公开(公告)号：US20230328996A1

公开(公告)日：2023-10-12

申请号：US18334590

申请日：2023-06-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tsu Ching Yang ,  Feng-Cheng Yang ,  Sheng-Chih Lai ,  Yu-Wei Jiang ,  Kuo-Chang Chiang ,  Hung-Chang Sun ,  Chen-Jun Wu ,  Chung-Te Lin

IPC: H10B51/20 ,  H10B51/30

CPC classification number: H10B51/20 ,  H10B51/30

Abstract: In some embodiments, the present disclosure relates to a method for forming a memory device, including forming a plurality of word line stacks respectively including a plurality of word lines alternatingly stacked with a plurality of insulating layers over a semiconductor substrate, forming a data storage layer along opposing sidewalls of the word line stacks, forming a channel layer along opposing sidewalls of the data storage layer, forming an inner insulating layer between inner sidewalls of the channel layer and including a first dielectric material, performing an isolation cut process including a first etching process through the inner insulating layer and the channel layer to form an isolation opening, forming an isolation structure filling the isolation opening and including a second dielectric material, performing a second etching process through the inner insulating layer on opposing sides of the isolation structure to form source/drain openings, and forming source/drain contacts in the source/drain openings.

公开(公告)号：US20230268438A1

公开(公告)日：2023-08-24

申请号：US18308791

申请日：2023-04-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yen-Chieh Huang ,  Po-Ting Lin ,  Hai-Ching Chen ,  Sai-Hooi Yeong ,  Yu-Ming Lin ,  Chung-Te Lin

IPC: H01L29/78 ,  H01L29/786 ,  H01L29/49 ,  H10B51/20

CPC classification number: H01L29/78391 ,  H01L29/78693 ,  H01L29/78642 ,  H01L29/4908 ,  H10B51/20

Abstract: A semiconductor device is described. The semiconductor device includes a substrate and a metal layer disposed on the substrate. A seed layer is formed on the metal layer. A ferroelectric gate layer is formed on the seed layer. A channel layer is formed over the ferroelectric gate layer. The seed layer is arranged to increase the orthorhombic phase fraction of the ferroelectric gate layer.

公开(公告)号：US20230263069A1

公开(公告)日：2023-08-17

申请号：US17672073

申请日：2022-02-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chang-Lin Yang ,  Sheng-Yuan Chang ,  Chung-Te Lin ,  Han-Ting Lin ,  Chien-Hua Huang

IPC: H01L43/08 ,  H01L27/22 ,  H01L43/12 ,  H01L43/02 ,  H01L43/10

CPC classification number: H01L43/08 ,  H01L27/228 ,  H01L43/12 ,  H01L43/02 ,  H01L43/10

Abstract: A method for manufacturing a memory device includes forming a first metal layer over a substrate, forming a magnetic tunnel junction (MTJ) layer stack over the first metal layer, forming a second metal layer over the MTJ layer stack, forming a hard mask layer over the second metal layer, performing a first etching process on the MTJ layer stack to form an MTJ structure and a redeposited layer on a sidewall of the MTJ structure, performing a second etching process to remove the redeposited layer, and performing a third etching process on the sidewall of the MTJ structure.

公开(公告)号：US11715546B2

公开(公告)日：2023-08-01

申请号：US17884634

申请日：2022-08-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chien-Hao Huang ,  Katherine H. Chiang ,  Cheng-Yi Wu ,  Chung-Te Lin

IPC: G11C29/00 ,  G11C29/38 ,  G11C11/16

CPC classification number: G11C29/38 ,  G11C11/1673 ,  G11C11/1675

Abstract: A method of testing a non-volatile memory (NVM) array includes obtaining a current distribution of a subset of NVM cells of the NVM array, the current distribution including first and second portions corresponding to respective logically high and low states of the subset of NVM cells, programming an entirety of the NVM cells of the NVM array to one of the logically high or low states, determining an initial bit error rate (BER) by performing first and second pass/fail (P/F) tests on each NVM cell of the NVM array, and using the current distribution to adjust the initial BER rate. Each of obtaining the current distribution, programming the entirety of the NVM cells, and performing the first and second P/F tests is performed while the NVM array is heated to a target temperature.

公开(公告)号：US11652148B2

公开(公告)日：2023-05-16

申请号：US17471736

申请日：2021-09-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Song-Fu Liao ,  Hai-Ching Chen ,  Chung-Te Lin

IPC: H01L21/28 ,  H01L29/66 ,  H01L27/11597 ,  H01L29/786 ,  H01L21/443 ,  H01L21/02 ,  H01L21/4757

CPC classification number: H01L29/40111 ,  H01L27/11597 ,  H01L29/66969 ,  H01L21/02642 ,  H01L21/443 ,  H01L21/47573 ,  H01L29/7869

Abstract: A method for manufacturing a semiconductor feature includes: alternatingly forming first and second dielectric layers on a semiconductor substrate along a vertical direction; forming multiple spaced-apart trenches penetrating the first and second dielectric layers; forming multiple support segments filling the trenches; removing the second dielectric layers to form multiple spaces; forming multiple conductive layers filling the spaces; removing the support segments to expose the conductive layers and the first dielectric layers; selectively forming a blocking layer covering the first dielectric layers outside of the conductive layers; forming multiple selectively-deposited sub-layers on the exposed conductive layers outside of the blocking layer and each connected to one of the conductive layers; forming multiple channel sub-layers on the selectively-deposited sub-layers outside of the blocking layer; removing the blocking layer; forming multiple isolation sub-layers filling the trenches; and forming multiple source/drain segments each connected to corresponding ones of the channel sub-layers.

公开(公告)号：US20230143625A1

公开(公告)日：2023-05-11

申请号：US17570028

申请日：2022-01-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yen-Chieh Huang ,  Po-Ting Lin ,  Song-Fu Liao ,  Hai-Ching Chen ,  Chung-Te Lin

IPC: H01L21/28 ,  H01L29/66 ,  H01L29/78 ,  H01L27/11585

CPC classification number: H01L29/40111 ,  H01L29/6684 ,  H01L29/78391 ,  H01L27/11585

Abstract: In some embodiments, the present disclosure relates to a method for forming an integrated circuit (IC), including forming a first electrode layer having a first metal over a substrate, performing a first atomic layer deposition (ALD) pulse that exposes the first electrode layer to oxygen atoms, exposing the first electrode layer to a first temperature, the first temperature causing the first electrode layer to react with the oxygen atoms to form a seed structure over the first electrode layer, and performing a series of ALD pulses at a second temperature to form a ferroelectric structure over the seed structure. The second temperature is less than the first temperature and the ferroelectric structure is configured to store a data state.

公开(公告)号：US11637203B2

公开(公告)日：2023-04-25

申请号：US17383423

申请日：2021-07-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Feng Yin ,  Chia-Jung Yu ,  Pin-Cheng Hsu ,  Chung-Te Lin

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/66 ,  H01L29/10 ,  H01L29/08

Abstract: A semiconductor device includes a transistor. The transistor includes a gate electrode, a channel layer, a gate dielectric layer, a first source/drain region and a second source/drain region and a first spacer. The channel layer is disposed on the gate electrode. The gate dielectric layer is located between the channel layer and the gate electrode. The first source/drain region and the second source/drain region are disposed on the channel layer at opposite sides of the gate electrode, and at least one of the first and second source/drain regions includes a first portion and a second portion between the first portion and the gate electrode. The first spacer is disposed on the channel layer. The first spacer is disposed on a first sidewall of the second portion of the at least one of the first and second source/drain regions, and the first portion is disposed on the first spacer.