公开(公告)号：US20170097894A1

公开(公告)日：2017-04-06

申请号：US14874842

申请日：2015-10-05

Applicant: Texas Instruments Incorporated

Inventor： Raguram Damodaran ,  Joseph Raymond Michael Zbiciak ,  Naveen Bhoria

IPC: G06F12/08 ,  G06F12/12

CPC classification number: G06F12/0888 ,  G06F12/0862 ,  G06F12/0897 ,  G06F12/12 ,  G06F12/121 ,  G06F2212/1021 ,  G06F2212/6022 ,  G06F2212/70

Abstract: The level one memory controller maintains a local copy of the cacheability bit of each memory attribute register. The level two memory controller is the initiator of all configuration read/write requests from the CPU. Whenever a configuration write is made to a memory attribute register, the level one memory controller updates its local copy of the memory attribute register.

公开(公告)号：US09298643B2

公开(公告)日：2016-03-29

申请号：US14728541

申请日：2015-06-02

Applicant: Texas Instruments Incorporated

Inventor： Jonathan (Son) Hung Tran ,  Raguram Damodaran ,  Abhijeet Ashok Chachad ,  Joseph Raymond Michael Zbiciak

IPC: G06F12/10 ,  G06F7/483 ,  G06F9/30 ,  H03M13/35 ,  H03M13/29 ,  G06F11/10 ,  G06F13/16 ,  G06F13/18 ,  H03K19/00 ,  G06F1/32 ,  H03K21/00 ,  G06F12/02 ,  G06F12/12 ,  G06F12/08 ,  G06F13/364

CPC classification number: G06F12/1081 ,  G06F1/3296 ,  G06F7/483 ,  G06F9/3012 ,  G06F11/1064 ,  G06F12/0246 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/12 ,  G06F13/1605 ,  G06F13/1652 ,  G06F13/1657 ,  G06F13/1663 ,  G06F13/18 ,  G06F13/364 ,  G06F2212/1021 ,  G06F2212/1032 ,  G06F2212/221 ,  G06F2212/2532 ,  G06F2212/283 ,  G06F2212/608 ,  H03K19/0016 ,  H03K21/00 ,  H03M13/2903 ,  H03M13/353 ,  Y02D10/124 ,  Y02D10/172 ,  Y02D50/20

Abstract: This invention optimizes DMA writes to directly addressable level two memory that is cached in level one and the line is valid and dirty. When the level two controller detects that a line is valid and dirty in level one, the level two memory need not update its copy of the data. Level one memory will replace the level two copy with a victim writeback at a future time. Thus the level two memory need not store write a copy. This limits the number of DMA writes to level two directly addressable memory and thus improves performance and minimizes dynamic power. This also frees the level two memory for other master/requestors.

Abstract translation: 本发明将DMA写入优化为直接可寻址的二级存储器，该存储器缓存在一级，并且该行是有效和脏的。 当二级控制器检测到一级线路有效且脏一级时，二级存储器不需要更新其数据副本。 一级记忆将在将来的时候用受害者回写替代第二级副本。 因此，二级内存不需要存储写入副本。 这将DMA写入次数限制在二级可直接寻址的存储器中，从而提高性能并最大限度地减少动态功耗。 这也释放了其他主/请求者的二级内存。

公开(公告)号：US09244837B2

公开(公告)日：2016-01-26

申请号：US13649269

申请日：2012-10-11

Applicant: Texas Instruments Incorporated

Inventor： Naveen Bhoria ,  Raguram Damodaran ,  Abhijeet Ashok Chachad

IPC: G06F12/00 ,  G06F12/08 ,  G06F12/12 ,  G06F13/28

CPC classification number: G06F12/0808 ,  G06F12/08 ,  G06F12/0811 ,  G06F12/0891 ,  G06F12/122 ,  G06F13/28 ,  G06F2212/1021 ,  G06F2212/62 ,  Y02D10/13

Abstract: A method to eliminate the delay of a block invalidate operation in a multi CPU environment by overlapping the block invalidate operation with normal CPU accesses, thus making the delay transparent. A range check is performed on each CPU access while a block invalidate operation is in progress, and an access that maps to within the address range of the block invalidate operation is treated as a cache miss to ensure that the requesting CPU will receive valid data.

Abstract translation: 通过将块无效操作与正常CPU访问重叠来消除多CPU环境中的块无效操作的延迟的方法，从而使得延迟变得透明。 在块无效操作正在进行时，对每个CPU访问执行范围检查，并将映射到块无效操作的地址范围内的访问视为高速缓存未命中，以确保请求的CPU将接收有效数据。

公开(公告)号：US08930783B2

公开(公告)日：2015-01-06

申请号：US13709188

申请日：2012-12-10

Applicant: Texas Instruments Incorporated

Inventor： Raguram Damodaran ,  Naveen Bhoria ,  Aman Kokrady

IPC: G01R31/28 ,  G11C29/12 ,  G01R31/3185 ,  G11C29/36

CPC classification number: G11C29/12 ,  G01R31/318519 ,  G01R31/318555 ,  G11C17/00 ,  G11C29/16 ,  G11C29/36 ,  G11C2029/0401

Abstract: A programmable Built In Self Test (pBIST) system used to test embedded memories where a plurality of memories requiring different testing conditions are incorporated in an SOC. The pBIST Read Only Memory storing the test setup data is organized to eliminate multiple instances of test setup data for similar embedded memories.

Abstract translation: 用于测试嵌入式存储器的可编程内建自测（pBIST）系统，其中需要不同测试条件的多个存储器被并入到SOC中。 存储测试设置数据的pBIST只读存储器被组织以消除类似的嵌入式存储器的测试设置数据的多个实例。

公开(公告)号：US20150006820A1

公开(公告)日：2015-01-01

申请号：US13973306

申请日：2013-08-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen Bhoria ,  Joseph Raymond Michael Zbiciak ,  Raguram Damodaran ,  Abhijeet Ashok Chachad

IPC: G06F12/08

CPC classification number: G06F12/0811

Abstract: Traffic output from a cache write-miss buffer is controlled by determining whether a predetermined condition is satisfied, and outputting an oldest entry from the buffer only in response to a determination that the predetermined condition is satisfied. Posting of a new entry to the buffer is insufficient to satisfy the predetermined condition.

Abstract translation: 通过确定是否满足预定条件来控制来自高速缓存写入 - 未命中缓冲器的流量输出，并且仅响应于满足预定条件的确定从缓冲器输出最旧的条目。 向缓冲器发送新条目不足以满足预定条件。

公开(公告)号：US20140164854A1

公开(公告)日：2014-06-12

申请号：US13709168

申请日：2012-12-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Raguram Damodaran ,  Naveen Bhoria ,  Aman Kokrady

IPC: G11C29/12

CPC classification number: G11C29/12 ,  G11C5/147 ,  G11C29/12005 ,  G11C29/16 ,  G11C2029/0401

Abstract: A programmable Built In Self Test (pBIST) system used to test embedded memories where the memories may be operating at a voltage domain different from the voltage domain of the pBIST. A plurality of buffer and synchronizing registers are used to avoid meta stable conditions caused by the time delays introduced by the voltage shifters required to bridge the various voltage domains.

Abstract translation: 用于测试嵌入式存储器的可编程内建自测（pBIST）系统，其中存储器可能在不同于pBIST的电压域的电压域上工作。 使用多个缓冲器和同步寄存器来避免由桥接各个电压域所需的电压移位器引入的时间延迟引起的元稳定条件。

公开(公告)号：US08582384B1

公开(公告)日：2013-11-12

申请号：US13918276

申请日：2013-06-14

Applicant: Texas Instruments Incorporated

Inventor： Abhijeet A. Chachad ,  Ramakrishnan Venkatasubramanian ,  Raguram Damodaran

IPC: G11C17/18

CPC classification number: G11C7/1039 ,  G11C7/22 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50012 ,  G11C2029/0401 ,  G11C2029/0409

Abstract: In an embodiment of the invention, an integrated circuit includes a pipelined memory array and a memory control circuit. The pipelined memory array contains a plurality of memory banks. Based partially on the read access time information of a memory bank, the memory control circuit is configured to select the number of clock cycles used during read latency.

公开(公告)号：US09021320B2

公开(公告)日：2015-04-28

申请号：US13709168

申请日：2012-12-10

Applicant: Texas Instruments Incorporated

Inventor： Raguram Damodaran ,  Naveen Bhoria ,  Aman Kokrady

IPC: G11C29/00 ,  G11C29/12 ,  G11C5/14 ,  G11C29/16 ,  G11C29/04

CPC classification number: G11C29/12 ,  G11C5/147 ,  G11C29/12005 ,  G11C29/16 ,  G11C2029/0401

Abstract: A programmable Built In Self Test (pBIST) system used to test embedded memories where the memories may be operating at a voltage domain different from the voltage domain of the pBIST. A plurality of buffer and synchronizing registers are used to avoid meta stable conditions caused by the time delays introduced by the voltage shifters required to bridge the various voltage domains.

Abstract translation: 用于测试嵌入式存储器的可编程内建自测（pBIST）系统，其中存储器可能在不同于pBIST的电压域的电压域上工作。 使用多个缓冲器和同步寄存器来避免由桥接各个电压域所需的电压移位器引入的时间延迟引起的元稳定条件。

公开(公告)号：US09009550B2

公开(公告)日：2015-04-14

申请号：US13709220

申请日：2012-12-10

Applicant: Texas Instruments Incorporated

Inventor： Raguram Damodaran ,  Naveen Bhoria ,  Aman Kokrady

IPC: G11C29/00 ,  G06F11/27 ,  G11C29/16 ,  G11C29/32 ,  G11C29/04

CPC classification number: G06F11/27 ,  G11C29/16 ,  G11C29/32 ,  G11C2029/0401

Abstract: A programmable Built In Self Test (pBIST) system used to test embedded memories where the memories under test are incorporated in a plurality of sub chips not integrated with the pBIST module. A distributed Data Logger is incorporated into each sub chip, communicating with the pBIST over serial and a compressed parallel data paths.

Abstract translation: 用于测试嵌入式存储器的可编程内置自测（pBIST）系统，其中被测存储器被并入未与pBIST模块集成的多个子芯片中。 分布式数据记录器被并入到每个子芯片中，通过串行和压缩的并行数据路径与pBIST进行通信。

公开(公告)号：US08977821B2

公开(公告)日：2015-03-10

申请号：US13660003

申请日：2012-10-25

Applicant: Texas Instruments Incorporated

Inventor： Naveen Bhoria ,  Raguram Damodaran

IPC: G06F12/08

CPC classification number: G06F12/0811 ,  G06F12/0891

Abstract: A method to eliminate the delay of multiple overlapping block invalidate operations in a multi CPU environment by overlapping the block invalidate operation with normal CPU accesses, thus making the delay transparent. The cache controller performing the block invalidate operation merges multiple overlapping requests into a parallel stream to eliminate execution delays. Cache operations other that block invalidate, such as block write back or block write back invalidate may also be merged into the execution stream.

Abstract translation: 通过将块无效操作与正常的CPU访问重叠来消除多CPU环境中多个重叠块无效操作的延迟的方法，从而使延迟透明。 执行块无效操作的高速缓存控制器将多个重叠的请求合并到并行流中以消除执行延迟。 缓存操作其他块无效，如块写回或块写回无效也可以合并到执行流中。