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    CMOS CASCODE POWER CELLS
    23.
    发明申请
    CMOS CASCODE POWER CELLS 有权
    CMOS CASCODE电源

    公开(公告)号：US20150015336A1

    公开(公告)日：2015-01-15

    申请号：US13939209

    申请日：2013-07-11

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Tzu-Jin YEH ,  Chewn-Pu JOU ,  Jun-De JIN ,  Hsieh-Hung HSIEH ,  Chia-Chung CHEN

    IPC: H03F3/213 ,  H01L21/8238

    CPC classification number: H03F3/213 ,  H01L21/8238 ,  H01L27/092 ,  H01L2924/3011 ,  H03F1/223

    Abstract: A circuit includes a first CMOS device forming a gain stage of a power amplifier and a second CMOS device forming a voltage buffer stage of the power amplifier. The first CMOS device includes a first doped well formed in a substrate, a first drain region and a first source region spaced laterally from one another in the first doped well, and a first gate structure formed over a first channel region in the first doped well. The second CMOS device includes a second doped well formed in the semiconductor substrate such that the first doped well and the second is disposed adjacent to the second doped well. A second drain region and a second source region are spaced laterally from one another in the second doped well, and a second gate structure formed over a second channel region in the second doped well.

    Abstract translation: 电路包括形成功率放大器的增益级的第一CMOS器件和形成功率放大器的电压缓冲级的第二CMOS器件。 第一CMOS器件包括形成在衬底中的第一掺杂阱，第一漏极区和在第一掺杂阱中彼此横向间隔开的第一源极区，以及形成在第一掺杂阱中的第一沟道区上的第一栅极结构 。 第二CMOS器件包括在半导体衬底中形成的第二掺杂阱，使得第一掺杂阱和第二掺杂阱邻近第二掺杂阱设置。 第二漏极区域和第二源极区域在第二掺杂阱中彼此横向隔开，第二栅极结构形成在第二掺杂阱中的第二沟道区域上。

    EDGE COUPLERS AND METHODS OF MAKING THE SAME
    24.
    发明申请
    EDGE COUPLERS AND METHODS OF MAKING THE SAME 有权

    公开(公告)号：US20240377590A1

    公开(公告)日：2024-11-14

    申请号：US18784541

    申请日：2024-07-25

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Min-Hsiang HSU ,  Chewn-Pu JOU ,  Chan-Hong CHERN ,  Cheng-Tse TANG ,  Yung-Jr HUNG ,  Lan-Chou CHO

    IPC: G02B6/30

    Abstract: Disclosed are edge couplers having a high coupling efficiency and low polarization dependent loss, and methods of making the edge couplers. In one embodiment, a semiconductor device for optical coupling is disclosed. The semiconductor device includes: a substrate; an optical waveguide over the substrate; and a plurality of layers over the optical waveguide. The plurality of layers includes a plurality of coupling pillars disposed at an edge of the semiconductor device. The plurality of coupling pillars form an edge coupler configured for optically coupling the optical waveguide to an optical fiber placed at the edge of the semiconductor device.

    EMBEDDED METAL INSULATOR METAL STRUCTURE
    30.
    发明申请
    EMBEDDED METAL INSULATOR METAL STRUCTURE 审中-公开

    公开(公告)号：US20190157108A1

    公开(公告)日：2019-05-23

    申请号：US15963725

    申请日：2018-04-26

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Wen-Shiang LIAO ,  Chewn-Pu JOU

    IPC: H01L21/48 ,  H01L49/02 ,  H01L23/31 ,  H01L23/498

    Abstract: The present disclosure describes a method of forming a metal insulator metal (MIM) decoupling capacitor that can be integrated (or embedded) into a 3D integrated circuit package such as, for example, a chip-on-wafer-on-substrate (CoWoS) chip package or an integrated fan-out (InFO) chip package. For example, the method includes providing a glass carrier with a protective layer over the glass carrier. The method also includes forming a capacitor on the protective layer by: forming a bottom metal layer on a portion of the protective layer; forming one or more first metal contacts and a second metal contact on the bottom metal layer, where the one or more first metal contacts have a width larger than the second metal contact; forming a dielectric layer on the one or more first metal contacts; and forming a top metal layer on the dielectric layer.

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