公开(公告)号：US20200319560A1

公开(公告)日：2020-10-08

申请号：US16905016

申请日：2020-06-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Hui WENG ,  Ching-Yu CHANG ,  Chin-Hsiang LIN

IPC: G03F7/40 ,  H01L21/027

Abstract: Methods for performing a lithography process are provided. The method for performing a lithography process includes forming a resist layer over a substrate and exposing a portion of the resist layer to form an exposed portion between unexposed portions. The method for performing a lithography process further includes developing the resist layer to remove the exposed portion of the resist layer such that an opening is formed between the unexposed portions and forming a post treatment coating material in the opening and over the unexposed portions of the resist layer. The method for performing a lithography process further includes reacting a portion of the unexposed portions of the resist layer with the post treatment coating material by performing a post treatment process and removing the post treatment coating material.

公开(公告)号：US20200006078A1

公开(公告)日：2020-01-02

申请号：US16240402

申请日：2019-01-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ru-Gun LIU ,  Chih-Ming LAI ,  Wei-Liang LIN ,  Yung-Sung YEN ,  Ken-Hsien HSIEH ,  Chin-Hsiang LIN

IPC: H01L21/311 ,  H01L21/027 ,  H01L21/768

Abstract: In a method of forming a groove pattern extending in a first axis in an underlying layer over a semiconductor substrate, a first opening is formed in the underlying layer, and the first opening is extended in the first axis by directional etching to form the groove pattern.

公开(公告)号：US20200004137A1

公开(公告)日：2020-01-02

申请号：US16287450

申请日：2019-02-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ru-Gun LIU ,  Chin-Hsiang LIN ,  Cheng-I HUANG ,  Chih-Ming LAI ,  Lai Chien WEN ,  Ken-Hsien HSIEH ,  Shih-Ming CHANG ,  Yuan-Te HOU

IPC: G03F1/42 ,  G03F1/50 ,  G03F1/68 ,  G03F7/20

Abstract: A photo mask for manufacturing a semiconductor device includes a first pattern extending in a first direction, a second pattern extending in the first direction and aligned with the first pattern, and a sub-resolution pattern extending in the first direction, disposed between an end of the first pattern and an end of the second pattern. A width of the first pattern and a width of the second pattern are equal to each other, and the first pattern and the second pattern are for separate circuit elements in the semiconductor device.

公开(公告)号：US20190206680A1

公开(公告)日：2019-07-04

申请号：US16228259

申请日：2018-12-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Han LAI ,  Chien-Wei WANG ,  Ching-Yu CHANG ,  Chin-Hsiang LIN

IPC: H01L21/033 ,  H01L21/02 ,  G03F7/09 ,  G03F7/11 ,  G03F7/20 ,  G03F7/16

Abstract: Provided is a material composition and method for substrate modification. A substrate is patterned to include a plurality of features. The plurality of features includes a first subset of features having one or more substantially inert surfaces. In various embodiments, a priming material is deposited over the substrate, over the plurality of features, and over the one or more substantially inert surfaces. By way of example, the deposited priming material bonds at least to the one or more substantially inert surfaces. Additionally, the deposited priming material provides a modified substrate surface. After depositing the priming material, a layer is spin-coated over the modified substrate surface, where the spin-coated layer is substantially planar.

公开(公告)号：US20190204730A1

公开(公告)日：2019-07-04

申请号：US16228339

申请日：2018-12-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun-Yue LIN ,  Hsuan-Chen CHEN ,  Chih-Cheng LIN ,  Hsin-Chang LEE ,  Yao-Ching KU ,  Wei-Jen LO ,  Anthony YEN ,  Chin-Hsiang LIN ,  Mark CHIEN

IPC: G03F1/62 ,  G03F1/24

CPC classification number: G03F1/62 ,  G03F1/24

Abstract: A method for fabricating a pellicle includes forming a first dielectric layer over a back surface of a substrate. After forming the first dielectric layer, and in some embodiments, a graphene layer is formed over a front surface of the substrate. In some examples, after forming the graphene layer, the first dielectric layer is patterned to form an opening in the first dielectric layer that exposes a portion of the back surface of the substrate. Thereafter, while using the patterned first dielectric layer as a mask, an etching process may be performed to the back surface of the substrate to form a pellicle having a pellicle membrane that includes the graphene layer.

公开(公告)号：US20190163046A1

公开(公告)日：2019-05-30

申请号：US16151300

申请日：2018-10-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hung-Wen CHO ,  Fu-Jye LIANG ,  Chun-Kuang CHEN ,  Chih-Tsung SHIH ,  Li-Jui CHEN ,  Po-Chung CHENG ,  Chin-Hsiang LIN

IPC: G03F1/24 ,  G03F1/36 ,  G03F7/20

Abstract: A method of controlling reticle masking blade positioning to minimize the impact on critical dimension uniformity includes determining a target location of a reticle masking blade relative to a reflective reticle and positioning the reticle masking blade at the target location. A position of the reticle masking blade is monitored during an imaging operation. The position of the reticle masking blade is compared with the target location and the position of the reticle masking blade is adjusted if the position of the reticle masking blade is outside a tolerance of the target location.

公开(公告)号：US20190137866A1

公开(公告)日：2019-05-09

申请号：US15906586

申请日：2018-02-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Wen CHO ,  Fu-Jye LIANG ,  Chun-Kuang CHEN ,  Chih-Tsung SHIH ,  Li-Jui CHEN ,  Po-Chung CHENG ,  Chin-Hsiang LIN

IPC: G03F1/64 ,  G03F7/22 ,  G03F7/20 ,  G03F1/22 ,  G06T7/00

Abstract: A reticle used for collecting information for image-error compensation is provided. The reticle includes a first black border structure and a second black border structure formed over a substrate. The first and second black borders are concentric with a center of the substrate. The reticle further includes a first image structure and a second image structure formed over the substrate. The first and second image structures each has patterns representing features to be patterned on a semiconductor wafer. In a direction away from the center of the substrate, the second image structure, the second black border structure, the first image structure and the first black border structure are arranged in order.

公开(公告)号：US20190122881A1

公开(公告)日：2019-04-25

申请号：US16021521

申请日：2018-06-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： An-Ren ZI ,  Chin-Hsiang LIN ,  Ching-Yu CHANG

IPC: H01L21/027 ,  H01L21/311 ,  G03F7/20

CPC classification number: H01L21/0274 ,  G03F7/70033 ,  H01L21/311

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a material layer over a substrate and forming a resist layer over the material layer. The resist layer includes an inorganic material and an auxiliary, and the inorganic material includes a plurality of metallic cores, and a plurality of first linkers bonded to the metallic cores. The method also includes exposing a portion of the resist layer by performing an exposure process, and the auxiliary reacts with the first linkers during the exposure process. The method further includes etching a portion of the resist layer to form a patterned resist layer and patterning the material layer by using the patterned resist layer as a mask. The method also includes removing the patterned resist layer.

公开(公告)号：US20190064673A1

公开(公告)日：2019-02-28

申请号：US15940107

申请日：2018-03-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Hui WENG ,  Ching-Yu CHANG ,  Chin-Hsiang LIN

IPC: G03F7/40 ,  H01L21/027

CPC classification number: G03F7/40 ,  G03F7/20 ,  G03F7/30 ,  H01L21/0273 ,  H01L21/0274

Abstract: Methods for performing a lithography process are provided. The method for performing a lithography process includes forming a resist layer over a substrate and exposing a portion of the resist layer to form an exposed portion between unexposed portions. The method for performing a lithography process further includes developing the resist layer to remove the exposed portion of the resist layer such that an opening is formed between the unexposed portions and forming a post treatment coating material in the opening and over the unexposed portions of the resist layer. The method for performing a lithography process further includes reacting a portion of the unexposed portions of the resist layer with the post treatment coating material by performing a post treatment process and removing the post treatment coating material.

公开(公告)号：US20150009499A1

公开(公告)日：2015-01-08

申请号：US14494621

申请日：2014-09-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Ming LIN ,  Wan-Lai CHEN ,  Chia-Hung HUANG ,  Chi-Ming YANG ,  Chin-Hsiang LIN

IPC: H01L21/68 ,  H01L21/683

CPC classification number: H01L21/681 ,  H01L21/268 ,  H01L21/67282 ,  H01L21/683 ,  H01L23/544 ,  H01L2223/54426 ,  H01L2223/54493 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A system for orienting a semiconductor wafer. The system includes a wafer retaining device configured to retain a semiconductor wafer, a light source configured to emit light toward an edge exclusion area of the wafer, and a lens configured to direct and focus light emitted from the light source at a subsurface first part of a first portion of the wafer to alter a crystalline structure of the subsurface first part and form a subsurface mark that is detectable using light of a predetermined wavelength, a predetermined transmittance through the wafer, and at a predetermined reflectance angle relative to an axis of rotation of the wafer and based on the predetermined wavelength.

Abstract translation: 一种用于定向半导体晶片的系统。 该系统包括被配置为保持半导体晶片的晶片保持装置，被配置为朝向晶片的边缘排除区域发光的光源，以及被配置为将来自光源的光从第一部分 晶片的第一部分，以改变地下第一部分的晶体结构，并形成可使用预定波长的光，通过晶片的预定透射率和相对于旋转轴线的预定反射角可检测的地下标记 并且基于预定波长。