公开(公告)号：US11948839B2

公开(公告)日：2024-04-02

申请号：US17516404

申请日：2021-11-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Chih-Hao Wang ,  Kuan-Lun Cheng

IPC: H01L21/8234 ,  H01L23/535 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L29/161 ,  H01L29/165

CPC classification number: H01L21/823418 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/535 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/161 ,  H01L29/165

Abstract: The present disclosure describes a method to reduce power consumption in a fin structure. For example, the method includes forming a first and a second semiconductor fins on a substrate with different heights. The method also includes forming insulating fins between and adjacent to the first and the second semiconductor fins. Further, the method includes forming a first and second epitaxial stacks with different heights on each of the first and second semiconductor fins.

公开(公告)号：US11923457B2

公开(公告)日：2024-03-05

申请号：US17850251

申请日：2022-06-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Yu Yang ,  Kai-Chieh Yang ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/08 ,  H01L21/311 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L21/31116 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66795

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a semiconductor fin disposed over a substrate, wherein the semiconductor fin includes a channel region and a source/drain region; a gate structure disposed over the channel region of the semiconductor fin, wherein the gate structure includes a gate spacer and a gate stack; a source/drain structure disposed over the source/drain region of the semiconductor fin; and a fin top hard mask vertically interposed between the gate spacer and the semiconductor fin, wherein the fin top hard mask includes a dielectric layer, and wherein a sidewall of the fin top hard mask directly contacts the gate stack, and another sidewall of the fin top hard mask directly contacts the source/drain structure.

公开(公告)号：US11901456B2

公开(公告)日：2024-02-13

申请号：US17838941

申请日：2022-06-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shi Ning Ju ,  Kuo-Cheng Chiang ,  Chih-Hao Wang ,  Kuan-Lun Cheng

IPC: H01L29/78 ,  H01L23/522 ,  H01L23/528 ,  H01L27/088 ,  H01L27/092 ,  H01L29/417 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/762

CPC classification number: H01L29/7851 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/5286 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/4175 ,  H01L29/41791 ,  H01L29/6681 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L21/76224 ,  H01L21/823418

Abstract: A semiconductor structure includes a power rail on a back side of the semiconductor structure, a first interconnect structure on a front side of the semiconductor structure, and a source feature, a drain feature, a first semiconductor fin, and a gate structure that are between the power rail and the first interconnect structure. The first semiconductor fin connects the source feature and the drain feature. The gate structure is disposed on a front surface and two side surfaces of the first semiconductor fin. The semiconductor structure further includes an isolation structure disposed between the power rail and the drain feature and between the power rail and the first semiconductor fin and a via penetrating through the isolation structure and connecting the source feature to the power rail.

公开(公告)号：US11862734B2

公开(公告)日：2024-01-02

申请号：US17717477

申请日：2022-04-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Chiang ,  Shi Ning Ju ,  Guan-Lin Chen ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L21/768 ,  H01L29/786 ,  H01L29/66 ,  H01L29/423 ,  H01L29/40 ,  H01L21/02

CPC classification number: H01L29/78696 ,  H01L21/0262 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/66545

Abstract: A semiconductor device includes a substrate, a channel member above the substrate, a gate structure engaging the channel member, an epitaxial feature in physical contact with the channel member, and a dielectric layer interposing the gate structure and the epitaxial feature. A sidewall surface of the dielectric layer facing the gate structure has a convex shape in a top view, and the convex shape has a center portion extending towards the gate structure.

公开(公告)号：US20230387010A1

公开(公告)日：2023-11-30

申请号：US18446113

申请日：2023-08-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu Huang ,  Li-Zhen Yu ,  Cheng-Chi Chuang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L23/528 ,  H01L29/40 ,  H01L29/417 ,  H01L29/78 ,  H01L27/092 ,  H01L27/088

CPC classification number: H01L23/5283 ,  H01L29/401 ,  H01L29/41775 ,  H01L29/7851 ,  H01L27/0924 ,  H01L27/0886 ,  H01L29/785 ,  H01L29/41791

Abstract: A method having a semiconductor substrate received and a first dielectric layer is formed over the semiconductor substrate. A trench is formed in the first dielectric layer. The trench is filled to form a conductive layer in the first dielectric layer. The conductive layer is segmented to form a first conductive feature and a second conductive feature separated from each other by a recess. The recess is filled with a second dielectric layer, such that one or both of the conductive features are end-capped by a portion of the first dielectric layer and a portion of the second dielectric layer.

公开(公告)号：US20230290687A1

公开(公告)日：2023-09-14

申请号：US18306629

申请日：2023-04-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Guan-Lin Chen ,  Kuo-Cheng Chiang ,  Shi Ning Ju ,  Jung-Chien Cheng ,  Chih-Hao Wang ,  Kuan-Lun Cheng

IPC: H01L21/8234 ,  H01L29/06 ,  H01L29/786 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L21/823412 ,  H01L29/0665 ,  H01L21/823418 ,  H01L29/78696 ,  H01L29/66545 ,  H01L29/0653 ,  H01L29/42392

Abstract: A method of forming a semiconductor device includes: forming a fin structure protruding above a substrate, where the fin structure comprises a fin and a layer stack overlying the fin, where the layer stack comprises alternating layers of a first semiconductor material and a second semiconductor material; forming a dummy gate structure over the fin structure; forming openings in the fin structure on opposing sides of the dummy gate structure, where the openings extend through the layer stack into the fin; forming a dielectric layer in bottom portions of the openings; and forming source/drain regions in the openings on the dielectric layer, where the source/drain regions are separated from the fin by the dielectric layer.

公开(公告)号：US11715781B2

公开(公告)日：2023-08-01

申请号：US16802396

申请日：2020-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wang-Chun Huang ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/51 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L27/088 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L29/513 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/78696

Abstract: A semiconductor device includes a substrate, two source/drain (S/D) regions over the substrate, a channel region between the two S/D regions and including a semiconductor material, a deposited capacitor material (DCM) layer over the channel region a dielectric layer over the DCM layer and a metallic gate electrode layer over the dielectric layer.

公开(公告)号：US20230197851A1

公开(公告)日：2023-06-22

申请号：US18168417

申请日：2023-02-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Hsing Hsu ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chih-Hao Wang ,  Sai-Hooi Yeong

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L29/785 ,  H01L29/66795 ,  H01L29/6684 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/7848 ,  H01L29/78391

Abstract: A semiconductor device includes a substrate. The semiconductor device includes a dielectric layer disposed over a portion of the substrate. The semiconductor device includes a diffusion blocking layer disposed over the dielectric layer. The diffusion blocking layer and the dielectric layer have different material compositions. The semiconductor device includes a ferroelectric layer disposed over the diffusion blocking layer.

公开(公告)号：US11682707B2

公开(公告)日：2023-06-20

申请号：US16948745

申请日：2020-09-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu Huang ,  Li-Zhen Yu ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L21/8234 ,  H01L29/51

CPC classification number: H01L29/41775 ,  H01L21/28114 ,  H01L21/823468 ,  H01L21/823475 ,  H01L29/4175 ,  H01L29/42376 ,  H01L29/6653 ,  H01L29/517

Abstract: A semiconductor device includes a metal gate structure having sidewall spacers disposed on sidewalls of the metal gate structure. In some embodiments, a top surface of the metal gate structure is recessed with respect to a top surface of the sidewall spacers. The semiconductor device may further include a metal cap layer disposed over and in contact with the metal gate structure, where a first width of a bottom portion of the metal cap layer is greater than a second width of a top portion of the metal cap layer. In some embodiments, the semiconductor device may further include a dielectric material disposed on either side of the metal cap layer, where the sidewall spacers and a portion of the metal gate structure are disposed beneath the dielectric material.

公开(公告)号：US11676819B2

公开(公告)日：2023-06-13

申请号：US17809847

申请日：2022-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Yu Wang ,  Zhi-Chang Lin ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/40 ,  H01L29/10 ,  H01L27/092 ,  H01L29/786 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/3213 ,  H01L21/3105

CPC classification number: H01L21/28123 ,  H01L21/31055 ,  H01L21/32136 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66545

Abstract: A semiconductor device includes a first fin, a second fin, a first gate electrode having a first portion that at least partially wraps around an upper portion of the first fin and a second portion that at least partially wraps around an upper portion of the second fin, a second gate electrode having a portion that at least partially wraps around the upper portion of the first fin, and a gate-cut feature having a first portion in the first gate electrode between the first and second portions of the first gate electrode. The gate-cut feature is at least partially filled with one or more dielectric materials. In a direction of a longitudinal axis of the first fin, the gate-cut feature has a second portion extending to a sidewall of the second gate electrode.