公开(公告)号：US20200279770A1

公开(公告)日：2020-09-03

申请号：US16876965

申请日：2020-05-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ping Tung ,  Jen Hung Wang ,  Shing-Chyang Pan

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

Abstract: A semiconductor device includes a substrate, a first conductive feature over a portion of the substrate, and an etch stop layer over the substrate and the first conductive feature. The etch stop layer includes a silicon-containing dielectric (SCD) layer and a metal-containing dielectric (MCD) layer over the SCD layer. The semiconductor device further includes a dielectric layer over the etch stop layer, and a second conductive feature in the dielectric layer. The second conductive feature penetrates the etch stop layer and electrically connects to the first conductive feature.

公开(公告)号：US20180350666A1

公开(公告)日：2018-12-06

申请号：US16043343

申请日：2018-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ping Tung ,  Jen Hung Wang ,  Shing-Chyang Pan

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L21/76829 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295

Abstract: A semiconductor device includes a substrate, a first conductive feature over a portion of the substrate, and an etch stop layer over the substrate and the first conductive feature. The etch stop layer includes a silicon-containing dielectric (SCD) layer and a metal-containing dielectric (MCD) layer over the SCD layer. The semiconductor device further includes a dielectric layer over the etch stop layer, and a second conductive feature in the dielectric layer. The second conductive feature penetrates the etch stop layer and electrically connects to the first conductive feature.

公开(公告)号：US09487864B2

公开(公告)日：2016-11-08

申请号：US14155695

申请日：2014-01-15

Applicant: Taiwan Semiconductor Manufacturing CO., LTD.

Inventor： Chih-Chien Chi ,  Szu-Ping Tung ,  Huang-Yi Huang ,  Ching-Hua Hsieh

IPC: H01L29/40 ,  C23C16/50 ,  H01L21/67 ,  H01L21/768

CPC classification number: C23C16/50 ,  C23C16/02 ,  C23C16/06 ,  C23C16/4401 ,  H01L21/02074 ,  H01L21/28562 ,  H01L21/28568 ,  H01L21/67184 ,  H01L21/67201 ,  H01L21/67207 ,  H01L21/68707 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/53238

Abstract: Before depositing a metal capping layer on a metal interconnect in a damascene structure, a remote plasma is used to reduce native oxide formed on the metal interconnect. Accordingly, a remote plasma reducing chamber is integrated in a processing platform for depositing a metal capping layer.

Abstract translation: 在镶嵌结构中的金属互连上沉积金属覆盖层之前，使用远程等离子体来减少在金属互连上形成的自然氧化物。 因此，远程等离子体还原室集成在用于沉积金属覆盖层的处理平台中。

公开(公告)号：US11991930B2

公开(公告)日：2024-05-21

申请号：US17984066

申请日：2022-11-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO, LTD.

Inventor： Jung-Tang Wu ,  Szu-Ping Tung ,  Szu-Hua Wu ,  Shing-Chyang Pan ,  Meng-Yu Wu

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/02 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80

CPC classification number: H10N50/01 ,  H10B61/22 ,  H10N50/80

Abstract: A structure includes a substrate, a transistor, a contact, an oxygen-free etch stop layer, an oxygen-containing etch stop layer, a dielectric layer, and a via. The transistor is on the substrate. The contact is on a source/drain region of the transistor. The oxygen-free etch stop layer spans the contact. The oxygen-containing etch stop layer extends along a top surface of the oxygen-free etch stop layer. The dielectric layer is over the oxygen-containing etch stop layer. The via passes through the dielectric layer, the oxygen-containing etch stop layer, and the oxygen-free etch stop layer and lands on the contact. The memory stack lands on the via.

公开(公告)号：US11804410B2

公开(公告)日：2023-10-31

申请号：US16810607

申请日：2020-03-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-De Ho ,  Han-Wei Wu ,  Pei-Sheng Tang ,  Meng-Jung Lee ,  Hua-Tai Lin ,  Szu-Ping Tung ,  Lan-Hsin Chiang

IPC: H01L21/66 ,  H01L21/67

CPC classification number: H01L22/12 ,  H01L21/67288

Abstract: A method for evaluation of thin film non-uniform stress using high order wafer warpage, the steps including measuring a net wafer warpage across a wafer area due to thin film deposition, fitting a two dimensional low-order polynomial to the wafer warpage measurements and subtracting the low-order polynomial from the net wafer warpage across the wafer area.

公开(公告)号：US20230275025A1

公开(公告)日：2023-08-31

申请号：US18313012

申请日：2023-05-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ping Tung ,  Chih-Chien Chi ,  Hung-Wen Su

IPC: H01L23/532 ,  H01L21/768 ,  H01L21/02 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/5329 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/02266 ,  H01L23/5222 ,  H01L23/53295 ,  H01L21/76802 ,  H01L21/76819 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/528 ,  H01L21/76849

Abstract: A semiconductor device and method of manufacture are provided which utilize an air gap to help isolate conductive structures within a dielectric layer. A first etch stop layer is deposited over the conductive structures, and the first etch stop layer is patterned to expose corner portions of the conductive structures. A portion of the dielectric layer is removed to form an opening. A second etch stop layer is deposited to line the opening, wherein the second etch stop layer forms a stepped structure over the corner portions of the conductive structures. Dielectric material is then deposited into the opening such that an air gap is formed to isolate the conductive structures.

公开(公告)号：US11651993B2

公开(公告)日：2023-05-16

申请号：US16876965

申请日：2020-05-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ping Tung ,  Jen Hung Wang ,  Shing-Chyang Pan

IPC: H01L23/48 ,  H01L23/52 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L23/485

CPC classification number: H01L21/76829 ,  H01L21/7682 ,  H01L21/76802 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/5329 ,  H01L23/53238 ,  H01L23/53295 ,  H01L21/76807 ,  H01L23/485 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53266

Abstract: A semiconductor device includes a substrate, a first conductive feature over a portion of the substrate, and an etch stop layer over the substrate and the first conductive feature. The etch stop layer includes a silicon-containing dielectric (SCD) layer and a metal-containing dielectric (MCD) layer over the SCD layer. The semiconductor device further includes a dielectric layer over the etch stop layer, and a second conductive feature in the dielectric layer. The second conductive feature penetrates the etch stop layer and electrically connects to the first conductive feature.

公开(公告)号：US11322396B2

公开(公告)日：2022-05-03

申请号：US16043343

申请日：2018-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ping Tung ,  Jen Hung Wang ,  Shing-Chyang Pan

IPC: H01L23/48 ,  H01L23/52 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L23/485

Abstract: A semiconductor device includes a substrate, a first conductive feature over a portion of the substrate, and an etch stop layer over the substrate and the first conductive feature. The etch stop layer includes a silicon-containing dielectric (SCD) layer and a metal-containing dielectric (MCD) layer over the SCD layer. The semiconductor device further includes a dielectric layer over the etch stop layer, and a second conductive feature in the dielectric layer. The second conductive feature penetrates the etch stop layer and electrically connects to the first conductive feature.

公开(公告)号：US10862026B2

公开(公告)日：2020-12-08

申请号：US16741557

申请日：2020-01-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jung-Tang Wu ,  Szu-Ping Tung ,  Szu-Hua Wu ,  Shing-Chyang Pan ,  Meng-Yu Wu

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/02

Abstract: A memory device includes a semiconductor substrate, a first dielectric layer, a metal contact, a metal nitride layer, an etch stop layer, a second dielectric layer, a metal via, and a memory stack. The first dielectric layer is over the semiconductor substrate. The metal contact passes through the first dielectric layer. The metal nitride layer spans the first dielectric layer and the metal contact. The etch stop layer extends along a top surface of the metal nitride layer, in which a thickness of the metal nitride layer is less than a thickness of the etch stop layer. The second dielectric layer is over the etch stop layer. The metal via passes through the second dielectric layer, the etch stop layer, and the metal nitride layer and lands on the metal contact. The memory stack is in contact with the metal via.

公开(公告)号：US09640428B2

公开(公告)日：2017-05-02

申请号：US15077761

申请日：2016-03-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Chien Chi ,  Chung-Chi Ko ,  Mei-Ling Chen ,  Huang-Yi Huang ,  Szu-Ping Tung ,  Ching-Hua Hsieh

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/528 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76868 ,  H01L21/76876 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53261 ,  H01L23/53266 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A self-aligned repairing process for a barrier layer is provided. A repair layer is formed by chemical vapor deposition using an organometallic compound as a precursor gas. The precursor gas adsorbed on a dielectric layer exposed by defects in a barrier layer is transformed to an insulating metal oxide layer, and the precursor gas adsorbed on the barrier layer is transformed to a metal layer.