公开(公告)号：US20210358825A1

公开(公告)日：2021-11-18

申请号：US17384923

申请日：2021-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Wei Chen ,  Li-Chung Kuo ,  Ying-Ching Shih ,  Szu-Wei Lu ,  Jing-Cheng Lin ,  Long Hua Lee ,  Kuan-Yu Huang

IPC: H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065

Abstract: A method for forming an underfill structure and semiconductor packages including the underfill structure are disclosed. In an embodiment, the semiconductor package may include a package including an integrated circuit die; an interposer bonded to the integrated circuit die by a plurality of die connectors; and an encapsulant surrounding the integrated circuit die. The semiconductor package may further include a package substrate bonded to the interposer by a plurality of conductive connectors; a first underfill between the package and the package substrate, the first underfill having a first coefficient of thermal expansion (CTE); and a second underfill surrounding the first underfill, the second underfill having a second CTE less than the first CTE.

公开(公告)号：US11164855B2

公开(公告)日：2021-11-02

申请号：US16572619

申请日：2019-09-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Weiming Chris Chen ,  Chi-Hsi Wu ,  Chih-Wei Wu ,  Kuo-Chiang Ting ,  Szu-Wei Lu ,  Shang-Yun Hou ,  Ying-Ching Shih ,  Hsien-Ju Tsou ,  Cheng-Chieh Li

IPC: H01L23/32 ,  H01L25/18 ,  H01L25/00 ,  H01L23/00 ,  H01L21/82 ,  H01L23/48 ,  H01L21/56 ,  H01L23/367

Abstract: A package structure includes a circuit element, a first semiconductor die, a second semiconductor die, a heat dissipating element, and an insulating encapsulation. The first semiconductor die and the second semiconductor die are located on the circuit element. The heat dissipating element connects to the first semiconductor die, and the first semiconductor die is between the circuit element and the heat dissipating element, where a sum of a first thickness of the first semiconductor die and a third thickness of the heat dissipating element is substantially equal to a second thickness of the second semiconductor die. The insulating encapsulation encapsulates the first semiconductor die, the second semiconductor die and the heat dissipating element, wherein a surface of the heat dissipating element is substantially leveled with the insulating encapsulation.

公开(公告)号：US11164824B2

公开(公告)日：2021-11-02

申请号：US16865432

申请日：2020-05-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Fu Tsai ,  Kung-Chen Yeh ,  Li-Chung Kuo ,  Szu-Wei Lu ,  Ying-Ching Shih

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78

Abstract: A package structure includes a circuit substrate and a semiconductor package. The semiconductor package is disposed on the circuit substrate, and includes a plurality of semiconductor dies, an insulating encapsulant and a connection structure. The insulating encapsulant comprises a first portion and a second portion protruding from the first portion, the first portion is encapsulating the plurality of semiconductor dies and has a planar first surface, and the second portion has a planar second surface located at a different level than the planar first surface. The connection structure is located over the first portion of the insulating encapsulant on the planar first surface, and located on the plurality of semiconductor dies, wherein the connection structure is electrically connected to the plurality of semiconductor dies and the circuit substrate.

公开(公告)号：US11152330B2

公开(公告)日：2021-10-19

申请号：US16385242

申请日：2019-04-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Chieh Li ,  Pu Wang ,  Chih-Wei Wu ,  Ying-Ching Shih ,  Szu-Wei Lu

IPC: H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L21/78 ,  H01L25/065 ,  H01L23/367 ,  H01L25/00

Abstract: A method for forming a semiconductor package structure includes stacking chips to form a chip stack over an interposer. The method also includes disposing a semiconductor die over the interposer. The method also includes filling a first encapsulating layer between the chips and surrounding the chip stack and the semiconductor die. The method also includes forming a second encapsulating layer covering the chip stack and the semiconductor die. The first encapsulating layer fills the gap between the chip stack and the semiconductor die.

公开(公告)号：US11024616B2

公开(公告)日：2021-06-01

申请号：US16413612

申请日：2019-05-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Wei Chen ,  Li-Chung Kuo ,  Long-Hua Lee ,  Szu-Wei Lu ,  Ying-Ching Shih ,  Kuan-Yu Huang

IPC: H01L25/11 ,  H01L23/538 ,  H01L23/498 ,  H01L25/00 ,  H01L23/31 ,  H01L25/10 ,  H01L23/00 ,  H01L21/56 ,  H01L23/29

Abstract: Provided is a package structure including at least two chips, an interposer, a first encapsulant, and a second encapsulant. The at least two chips are disposed side by side and bonded to the interposer by a plurality of connectors. The first encapsulant is disposed on the interposer and filling in a gap between the at least two chips. The second encapsulant encapsulates the plurality of connectors and surrounding the at least two chips, wherein the second encapsulant is in contact with the first encapsulant sandwiched between the at least two chips, and a material of the second encapsulant has a coefficient of thermal expansion (CTE) larger than a CTE of a material of the first encapsulant. A method of manufacturing a package structure is also provided.

公开(公告)号：US10510732B2

公开(公告)日：2019-12-17

申请号：US15854755

申请日：2017-12-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Ju Tsou ,  Chih-Wei Wu ,  Jing-Cheng Lin ,  Pu Wang ,  Szu-Wei Lu ,  Ying-Ching Shih

IPC: H01L25/10 ,  H01L25/00 ,  H01L21/48 ,  H01L23/00 ,  H01L23/538

Abstract: Provided are a PoP device and a method of manufacturing the same. The PoP device includes a first package structure and a second package structure. The first package structure includes a die, a through integrated fan-out via (TIV), an encapsulant, and a film. The TIV is aside the die. The encapsulant encapsulates sidewalls of the die and sidewalls of the TIV. The film is over the TIV and the encapsulant, and aside the die. The second package structure is connected to the first package structure through a connector. The connector penetrates through the film to electrically connected to the TIV.

公开(公告)号：US20190103387A1

公开(公告)日：2019-04-04

申请号：US15854755

申请日：2017-12-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Ju Tsou ,  Chih-Wei Wu ,  Jing-Cheng Lin ,  Pu Wang ,  Szu-Wei Lu ,  Ying-Ching Shih

IPC: H01L25/10 ,  H01L25/00 ,  H01L21/48 ,  H01L23/00 ,  H01L23/538

Abstract: Provided are a PoP device and a method of manufacturing the same. The PoP device includes a first package structure and a second package structure. The first package structure includes a die, a through integrated fan-out via (TIV), an encapsulant, and a film. The TIV is aside the die. The encapsulant encapsulates sidewalls of the die and sidewalls of the TIV. The film is over the TIV and the encapsulant, and aside the die. The second package structure is connected to the first package structure through a connector. The connector penetrates through the film to electrically connected to the TIV.

公开(公告)号：US20190096851A1

公开(公告)日：2019-03-28

申请号：US15716506

申请日：2017-09-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Hang Liao ,  Chih-Wei Wu ,  Jing-Cheng Lin ,  Szu-Wei Lu ,  Ying-Ching Shih

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L21/568 ,  H01L21/56 ,  H01L21/6835 ,  H01L23/3128 ,  H01L25/065 ,  H01L2221/68345

Abstract: A package structure and a method of manufacturing the same are provided. The package structure includes a first die, a second die, a first encapsulant, a bridge, an underfill layer and a RDL structure. The first die and the second die are placed side by side. The first encapsulant encapsulates sidewalls of the first die and sidewalls of the second die. The bridge electrically connects the first die and the second die through two conductive bumps. The underfill layer fills the space between the bridge and the first die, between the bridge and the second die, and between the bridge and a portion of the first encapsualnt. The RDL structure is located over the bridge and electrically connected to the first die and the second die though a plurality of TIVs. The bottom surfaces of the two conductive bumps are level with a bottom surface of the underfill layer.

公开(公告)号：US20180197826A1

公开(公告)日：2018-07-12

申请号：US15911765

申请日：2018-03-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Wu ,  Ying-Ching Shih ,  Szu-Wei Lu ,  Jing-Cheng Lin

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/48

CPC classification number: H01L23/562 ,  H01L23/145 ,  H01L23/147 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/10135 ,  H01L2224/11464 ,  H01L2224/13012 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13562 ,  H01L2224/13582 ,  H01L2224/13644 ,  H01L2224/13664 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81007 ,  H01L2224/81139 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/1421 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1437 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/37001 ,  H01L2924/014 ,  H01L2924/00012

Abstract: Some embodiments of the present disclosure relate to an integrated circuit. The integrated circuit has a first semiconductor die and a second semiconductor die. The first semiconductor die is bonded to the second semiconductor die by one or more bonding structures. A first plurality of support structures are disposed between the first semiconductor die and the second semiconductor die. The first plurality of support structures are spaced apart from the one or more bonding structures. The first plurality of support structures are configured to hold together the first semiconductor die and the second semiconductor die.

公开(公告)号：US20250105086A1

公开(公告)日：2025-03-27

申请号：US18471739

申请日：2023-09-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yen Lan ,  Chih-Chien Pan ,  Pu Wang ,  Li-Hui Cheng ,  Ying-Ching Shih

IPC: H01L23/367 ,  H01L23/00 ,  H01L25/16 ,  H01L25/18 ,  H10B80/00

Abstract: Various embodiments include integrated circuit packages and methods of forming integrated circuit packages. In an embodiment, a device includes: a package substrate; an integrated circuit device attached to the package substrate; a stiffener ring around the integrated circuit device and attached to the package substrate; a lid attached to the stiffener ring; a channel connected to an area between the lid and the integrated circuit device, the channel extending along at least one side of the integrated circuit device in a top-down view; and a thermal interface material in the channel and in the area between the lid and the integrated circuit device.