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    Memory array including epitaxial source lines and bit lines
    22.
    发明授权
    Memory array including epitaxial source lines and bit lines 有权

    公开(公告)号：US11974441B2

    公开(公告)日：2024-04-30

    申请号：US17138152

    申请日：2020-12-30

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Chih-Yu Chang ,  Chi On Chui ,  Yu-Ming Lin

    IPC: H10B51/20 ,  H01L29/06 ,  H10B51/10

    CPC classification number: H10B51/20 ,  H01L29/0653 ,  H01L29/0669 ,  H10B51/10

    Abstract: A 3D memory array in which epitaxial source/drain regions which are horizontally merged and vertically unmerged are used as source lines and bit lines and methods of forming the same are disclosed. In an embodiment, a memory array includes a first channel region over a semiconductor substrate; a first epitaxial region electrically coupled to the first channel region; a second epitaxial region directly over the first epitaxial region in a direction perpendicular to a major surface of the semiconductor substrate; a dielectric material between the first epitaxial region and the second epitaxial region, the second epitaxial region being isolated from the first epitaxial region by the dielectric material; a gate dielectric surrounding the first channel region; and a gate electrode surrounding the gate dielectric.

    Memory Array Staircase Structure
    26.
    发明公开
    Memory Array Staircase Structure 审中-公开

    公开(公告)号：US20230377624A1

    公开(公告)日：2023-11-23

    申请号：US18362685

    申请日：2023-07-31

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Meng-Han Lin ,  Han-Jong Chia ,  Sheng-Chen Wang ,  Feng-Cheng Yang ,  Yu-Ming Lin ,  Chung-Te Lin

    IPC: G11C8/14 ,  H01L21/822 ,  H10B51/20 ,  H10B99/00

    CPC classification number: G11C8/14 ,  H01L21/8221 ,  H10B51/20 ,  H10B99/00

    Abstract: Routing arrangements for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a memory array includes a first word line extending from a first edge of the memory array in a first direction, the first word line having a length less than a length of a second edge of the memory array perpendicular to the first edge of the memory array; a second word line extending from a third edge of the memory array opposite the first edge of the memory array, the second word line extending in the first direction, the second word line having a length less than the length of the second edge of the memory array; a memory film contacting the first word line; and an OS layer contacting a first source line and a first bit line, the memory film being disposed between the OS layer and the first word line.

    Memory array staircase structure
    28.
    发明授权
    Memory array staircase structure 有权

    公开(公告)号：US11776602B2

    公开(公告)日：2023-10-03

    申请号：US17814341

    申请日：2022-07-22

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Meng-Han Lin ,  Han-Jong Chia ,  Sheng-Chen Wang ,  Feng-Cheng Yang ,  Yu-Ming Lin ,  Chung-Te Lin

    IPC: G11C8/14 ,  H01L21/822 ,  H10B51/20 ,  H10B99/00

    CPC classification number: G11C8/14 ,  H01L21/8221 ,  H10B51/20 ,  H10B99/00

    Abstract: Routing arrangements for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a memory array includes a first word line extending from a first edge of the memory array in a first direction, the first word line having a length less than a length of a second edge of the memory array perpendicular to the first edge of the memory array; a second word line extending from a third edge of the memory array opposite the first edge of the memory array, the second word line extending in the first direction, the second word line having a length less than the length of the second edge of the memory array; a memory film contacting the first word line; and an OS layer contacting a first source line and a first bit line, the memory film being disposed between the OS layer and the first word line.

    Semiconductor devices including ferroelectric memory and methods of forming the same
    29.
    发明授权
    Semiconductor devices including ferroelectric memory and methods of forming the same 有权

    公开(公告)号：US11727976B2

    公开(公告)日：2023-08-15

    申请号：US17814755

    申请日：2022-07-25

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chenchen Wang ,  Sai-Hooi Yeong ,  Chi On Chui ,  Yu-Ming Lin

    IPC: H01L29/78 ,  H01L29/51 ,  G11C11/22

    CPC classification number: G11C11/221 ,  H01L29/516 ,  H01L29/78391

    Abstract: A semiconductor device including a capacitor, with a memory film isolating a first electrode from a contact, formed over a transistor and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a gate stack over a semiconductor substrate; a capacitor over the gate stack, the capacitor including a first electrode extending along a top surface of the gate stack, the first electrode being U-shaped; a first ferroelectric layer over the first electrode; and a second electrode over the first ferroelectric layer, a top surface of the second electrode being level with a top surface of the first ferroelectric layer, and the top surface of the first ferroelectric layer and the top surface of the second electrode being disposed further from the semiconductor substrate than a topmost surface of the first electrode.

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