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42 条记录 (耗时 0.021 秒)

    Aluminum sputtering while biasing wafer
    22.
    发明授权
    Aluminum sputtering while biasing wafer 失效
    铝溅射同时偏置晶圆

    公开(公告)号：US07378002B2

    公开(公告)日：2008-05-27

    申请号：US11209328

    申请日：2005-08-23

    申请人： Wei Ti Lee ,  Ted Guo ,  Sang-Ho Yu

    发明人： Wei Ti Lee ,  Ted Guo ,  Sang-Ho Yu

    IPC分类号： C23C14/35 ,  H01L21/44

    CPC分类号： C23C14/185 ,  C23C14/025 ,  C23C14/046 ,  C23C14/345

    摘要： An aluminum sputtering process including RF biasing the wafer and a two-step aluminum fill process and apparatus used therefor to fill aluminum into a narrow via hole by sputtering under two distinctly different conditions, preferably in two different plasma sputter reactors. The first step includes sputtering a high fraction of ionized aluminum atoms onto a relatively cold wafer, e.g., held at less than 150° C., and relatively highly biased to attract aluminum atoms into the narrow holes and etch overhangs. The second step includes more neutral sputtering onto a relatively warm wafer, e.g. held at greater than 250° C., and substantially unbiased to provide a more isotropic and uniform aluminum flux. The magnetron scanned about the back of the aluminum target may be relatively small and unbalanced in the first step and relatively large and balanced in the second.

    摘要翻译： 一种铝溅射工艺，包括RF偏置晶片和两步铝填充工艺和装置，用于在两个明显不同的条件下，优选在两个不同的等离子体溅射反应器中通过溅射将铝填充到窄通孔中。 第一步包括将大部分电离铝原子溅射到相对冷的晶片上，例如保持在小于150℃，并且相当高的偏压以将铝原子吸引到窄孔中并蚀刻突出端。 第二步包括在相对温暖的晶片上的更中性的溅射，例如 保持在大于250℃，并且基本上无偏差以提供更多的各向同性和均匀的铝通量。 围绕铝靶的背面扫描的磁控管可能在第一步骤中相对较小并且不平衡，而在第二步中相对较大且平衡。

    Blanket-selective chemical vapor deposition using an ultra-thin nucleation layer
    24.
    发明授权
    Blanket-selective chemical vapor deposition using an ultra-thin nucleation layer 失效
    使用超薄成核层的毯选择性化学气相沉积

    公开(公告)号：US6066358A

    公开(公告)日：2000-05-23

    申请号：US611108

    申请日：1996-03-05

    申请人： Ted Guo ,  Liang Chen ,  Fusen Chen ,  Roderick C. Mosely

    发明人： Ted Guo ,  Liang Chen ,  Fusen Chen ,  Roderick C. Mosely

    IPC分类号： H01L21/285 ,  C23C14/56 ,  C23C16/54 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/677 ,  H01L21/768 ,  B05D5/12 ,  C23C14/04 ,  C23C16/04 ,  C23C16/06

    CPC分类号： H01L21/76876 ,  C23C14/568 ,  C23C16/54 ,  H01L21/32051 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76879

    摘要： The present invention relates generally to an improved apparatus and process for providing uniform step coverage on a substrate and planarization of conducting layers to form continuous, void-free interconnects in sub-half micron, high aspect ratio aperture width applications and highly oriented conducting layers. In one aspect of the invention, a dielectric layer is formed over a conducting or semiconducting layer and etched to form an aperture exposing the underlying conducting or semiconducting layer on the aperture floor. An ultra-thin nucleation layer is then deposited by physical vapor deposition onto the field of the dielectric layer. A CVD metal layer is then deposited onto the structure to achieve selective deposition on the floor of the aperture, while preferably also forming a highly oriented blanket layer on the field. The present apparatus and process reduce the number of steps necessary to fabricate CVD metal interconnects and layers that are substantially void-free and planarized. The metallization process is preferably carried out in an integrated processing system that includes both a PVD and CVD processing chamber so that once the substrate is introduced into a vacuum environment, the metallization of the apertures to form vias and contacts occurs without the formation of oxides between the layers.

    摘要翻译： 本发明一般涉及一种改进的装置和方法，用于在衬底上提供均匀的台阶覆盖和导电层的平坦化，以形成半微米，高纵横比孔径宽度应用和高度取向导电层的连续的无空隙互连。 在本发明的一个方面，电介质层形成在导电或半导体层之上，并被蚀刻以形成露出孔底板上下面的导电或半导体层的孔。 然后通过物理气相沉积将超薄成核层沉积到介电层的场上。 然后将CVD金属层沉积到结构上以实现孔的地板上的选择性沉积，同时优选地还在场上形成高度取向的覆盖层。 本装置和工艺减少了制造基本上无空隙和平坦化的CVD金属互连和层所需的步骤数量。 金属化处理优选在包括PVD和CVD处理室的一体化处理系统中进行，使得一旦将衬底引入真空环境中，孔的金属化形成通孔和接触，而不会在两者之间形成氧化物之间 层。

    Deposition film orientation and reflectivity improvement using a self-aligning ultra-thin layer
    27.
    发明授权
    Deposition film orientation and reflectivity improvement using a self-aligning ultra-thin layer 失效
    使用自对准超薄层的沉积膜取向和反射率提高

    公开(公告)号：US6120844A

    公开(公告)日：2000-09-19

    申请号：US622941

    申请日：1996-03-27

    申请人： Liang Chen ,  Ted Guo ,  Fusen Chen ,  Roderick C. Mosely

    发明人： Liang Chen ,  Ted Guo ,  Fusen Chen ,  Roderick C. Mosely

    IPC分类号： H01L21/28 ,  C23C14/56 ,  C23C16/54 ,  H01L21/02 ,  H01L21/203 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/677 ,  H01L21/768 ,  C23C14/34 ,  C23C16/06 ,  C23C16/22

    CPC分类号： H01L21/76876 ,  C23C14/568 ,  C23C16/54 ,  H01L21/32051 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76879

    摘要： The present invention relates generally to an improved apparatus and process to provide a thin self-aligning layer prior to forming a conducting film layer thereover to improve the film characteristics and deposition coverage. In one aspect of the invention, a dielectric layer is formed over a conducting or semiconducting layer and etched to form an aperture exposing the underlying conducting or semiconducting layer on the aperture floor. An ultra-thin nucleation layer is then deposited by either vapor deposition or chemical vapor deposition onto the field of the dielectric layer. A CVD metal layer is then deposited onto the structure to achieve selective deposition on the floor of the aperture, while preferably also forming a highly oriented blanket layer on the field. In another aspect of the invention, a thin, self-aligning layer is formed over a barrier layer prior to deposition of a conducting film thereover. It is believed that the self-aligning layer enhances the reflectivity of the films by improving the crystal structure in the resulting film and provides improved electromigration performance by providing crystal orientation. The process is preferably carried out in an integrated processing system that includes both a PVD and CVD processing chamber so that once the substrate is introduced into a vacuum environment, the process occurs without the formation of oxides between the layers.

    摘要翻译： 本发明一般涉及在形成导电膜层之前提供薄的自对准层以改善膜特性和沉积覆盖的改进的装置和工艺。 在本发明的一个方面，电介质层形成在导电或半导体层之上，并被蚀刻以形成露出孔底板上下面的导电或半导体层的孔。 然后通过气相沉积或化学气相沉积将超薄成核层沉积到电介质层的场上。 然后将CVD金属层沉积到结构上以实现孔的地板上的选择性沉积，同时优选地还在场上形成高度取向的覆盖层。 在本发明的另一方面，在其上沉积导电膜之前，在阻挡层上方形成薄的自对准层。 据认为，通过改善所得膜中的晶体结构，自对准层增强了膜的反射率，并通过提供<111>晶体取向来提供改善的电迁移性能。 该方法优选在包括PVD和CVD处理室的集成处理系统中进行，使得一旦将基底引入真空环境中，则该过程发生而不在层之间形成氧化物。

    Modulating surface morphology of barrier layers
    28.
    发明授权
    Modulating surface morphology of barrier layers 失效
    调制阻挡层的表面形态

    公开(公告)号：US5956608A

    公开(公告)日：1999-09-21

    申请号：US667842

    申请日：1996-06-20

    申请人： Nitin Khurana ,  Ted Guo

    发明人： Nitin Khurana ,  Ted Guo

    IPC分类号： H01L21/768 ,  H01L21/28 ,  H01L21/306

    CPC分类号： H01L21/76865 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76862 ,  Y10S438/906

    摘要： A process for fabricating electronic devices which includes the steps of providing a structure that includes a substrate with an overlying dielectric layer having one or more contact holes and/or vias formed therein; depositing a barrier layer over the structure so that the barrier layer penetrates into the contact holes and/or vias; plasma etching the deposited barrier layer so as to modify its surface morphology; and after modifying the surface morphology of the deposited barrier layer, depositing a metalization layer over the barrier layer. A two-step preclean to facet upper corners of the holes and/or vias and to clean bottoms of the holes and/or vias is performed prior to the deposition of the barrier layer.

    摘要翻译： 一种用于制造电子器件的方法，包括以下步骤：提供包括具有其中形成有一个或多个接触孔和/或通孔的上覆电介质层的衬底的结构; 在结构上沉积阻挡层，使得阻挡层渗透到接触孔和/或通孔中; 等离子体蚀刻沉积的阻挡层以改变其表面形态; 并且在改变沉积的阻挡层的表面形态之后，在阻挡层上沉积金属化层。 在沉积阻挡层之前，先进行将两个孔和/或通孔的上角分开并清洁孔和/或通孔的底部的两步预清洗。

    Aluminum contact integration on cobalt silicide junction
    30.
    发明授权
    Aluminum contact integration on cobalt silicide junction 失效
    硅化钴接头上的铝接触集成

    公开(公告)号：US07867900B2

    公开(公告)日：2011-01-11

    申请号：US12240816

    申请日：2008-09-29

    申请人： Wei Ti Lee ,  Mohd Fadzli Anwar Hassan ,  Ted Guo ,  Sang-Ho Yu

    发明人： Wei Ti Lee ,  Mohd Fadzli Anwar Hassan ,  Ted Guo ,  Sang-Ho Yu

    IPC分类号： H01L21/44

    CPC分类号： H01L23/53214 ,  H01L21/02068 ,  H01L21/28518 ,  H01L21/76876 ,  H01L21/76877 ,  H01L23/485 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Embodiments herein provide methods for forming an aluminum contact on a cobalt silicide junction. In one embodiment, a method for forming materials on a substrate is provided which includes forming a cobalt silicide layer on a silicon-containing surface of the substrate during a silicidation process, forming a fluorinated sublimation film on the cobalt silicide layer during a plasma process, heating the substrate to a sublimation temperature to remove the fluorinated sublimation film, depositing a titanium-containing nucleation layer over the cobalt silicide layer, and depositing an aluminum-containing material over the titanium-containing nucleation layer. In one example, the method further provides forming the cobalt silicide layer by depositing a cobalt-containing layer on the silicon-containing surface, heating the substrate during a rapid thermal annealing (RTA) process, etching away any remaining portions of the cobalt-containing layer from the substrate, and subsequently heating the substrate during another RTA process.

    摘要翻译： 本文的实施方案提供了在钴硅化物结上形成铝接触的方法。 在一个实施例中，提供了一种在衬底上形成材料的方法，包括在硅化过程中在衬底的含硅表面上形成钴硅化物层，在等离子体工艺期间在硅化钴层上形成氟化升华膜， 将基板加热到升华温度以除去氟化升华膜，在硅化钴层上沉积含钛成核层，并在含钛成核层上沉积含铝材料。 在一个实例中，该方法还提供通过在含硅表面上沉积含钴层来形成钴硅化物层，在快速热退火（RTA）工艺中加热衬底，蚀刻掉含钴的剩余部分 层，然后在另一RTA工艺期间加热衬底。