公开(公告)号：US06777277B2

公开(公告)日：2004-08-17

申请号：US10205605

申请日：2002-07-26

申请人： Tetsuro Asano ,  Katsuaki Onoda ,  Yoshibumi Nakajima ,  Shigeyuki Murai ,  Hisaaki Tominaga ,  Koichi Hirata ,  Mikito Sakakibara ,  Hidetoshi Ishihara

发明人： Tetsuro Asano ,  Katsuaki Onoda ,  Yoshibumi Nakajima ,  Shigeyuki Murai ,  Hisaaki Tominaga ,  Koichi Hirata ,  Mikito Sakakibara ,  Hidetoshi Ishihara

IPC分类号： H01L21338

CPC分类号： H01L29/66143 ,  H01L24/05 ,  H01L29/872 ,  H01L2224/04042 ,  H01L2224/45144 ,  H01L2224/4847 ,  H01L2924/14 ,  H01L2924/00

摘要： A Schottky barrier diode has a Schottky contact region formed in an n epitaxial layer disposed on a GaAs substrate and an ohmic electrode surrounding the Schottky contact region. The ohmic electrode is disposed directly on an impurity-implanted region formed on the substrate. An insulating region is formed through the n epitaxial layer so that an anode bonding pad is isolated form other elements of the device at a cathode voltage. The planar configuration of this device does not include the conventional polyimide layer, and thus has a better high frequency characteristics than conventional devices.

摘要翻译： 肖特基势垒二极管具有形成在设置在GaAs衬底上的n外延层中的肖特基接触区域和围绕肖特基接触区域的欧姆电极。 欧姆电极直接设置在形成在基板上的杂质注入区域上。 通过n外延层形成绝缘区域，使得阳极接合焊盘在阴极电压下与器件的其它元件隔离。 该器件的平面结构不包括传统的聚酰亚胺层，因此具有比常规器件更好的高频特性。

公开(公告)号：US06727559B2

公开(公告)日：2004-04-27

申请号：US10177762

申请日：2002-06-24

申请人： Tetsuro Asano ,  Masahiro Uekawa ,  Koichi Hirata ,  Mikito Sakakibara

发明人： Tetsuro Asano ,  Masahiro Uekawa ,  Koichi Hirata ,  Mikito Sakakibara

IPC分类号： H01L2976

CPC分类号： H01L24/06 ,  H01L23/4824 ,  H01L24/45 ,  H01L29/41758 ,  H01L29/42312 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05599 ,  H01L2224/0603 ,  H01L2224/45015 ,  H01L2224/45117 ,  H01L2224/45144 ,  H01L2224/45155 ,  H01L2224/48091 ,  H01L2224/4911 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12032 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/01032 ,  H01L2924/00

摘要： A local oscillation FET has a source connecting pad, a drain connecting pad and a gate connecting pad. The source connecting pad occupies one corner of a substrate, and the drain and gate connecting pads are placed at the neighboring corners so that the three connecting pads form an L shape on the substrate. As a modification to this configuration, another source connecting pad is placed at the remaining corner of the substrate so that the drain and gate connecting pads are shielded from each other by the two source connecting pads. These device configurations contribute to size reduction of the local oscillation FET.

摘要翻译： 本地振荡FET具有源极连接焊盘，漏极连接焊盘和栅极连接焊盘。 源极连接焊盘占据衬底的一个角，并且漏极和栅极连接焊盘被放置在相邻的拐角处，使得三个连接焊盘在衬底上形成L形。 作为该配置的修改，另一个源极连接焊盘放置在衬底的其余角部处，使得漏极和栅极连接焊盘通过两个源极连接焊盘彼此屏蔽。 这些器件配置有助于本地振荡FET的尺寸减小。

公开(公告)号：US08742506B2

公开(公告)日：2014-06-03

申请号：US13475375

申请日：2012-05-18

申请人： Tetsuro Asano ,  Mikito Sakakibara ,  Toshikazu Hirai

发明人： Tetsuro Asano ,  Mikito Sakakibara ,  Toshikazu Hirai

IPC分类号： H01L29/861

CPC分类号： H01L27/0255 ,  H01L24/48 ,  H01L27/0248 ,  H01L27/0288 ,  H01L29/66098 ,  H01L29/80 ,  H01L29/812 ,  H01L29/861 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2224/85399 ,  H01L2224/05599

摘要： With a microwave FET, an incorporated Schottky junction capacitance or PN junction capacitance is small and such a junction is weak against static electricity. However, with a microwave device, the method of connecting a protecting diode cannot be used since this method increases the parasitic capacitance and causes degradation of the high-frequency characteristics. In order to solve the above problems, a protecting element, having a first n+-type region-insulating region-second n+-type region arrangement is connected in parallel between two terminals of a protected element having a PN junction, Schottky junction, or capacitor. Since discharge can be performed between the first and second n+ regions that are adjacent each other, electrostatic energy that would reach the operating region of an FET can be attenuated without increasing the parasitic capacitance.

摘要翻译： 使用微波FET，结合的肖特基结电容或PN结电容小，并且这种结对静电弱。 然而，利用微波装置，不能使用连接保护二极管的方法，因为这种方法增加了寄生电容并导致高频特性的劣化。 为了解决上述问题，具有第一n +型区域 - 第二n +型区域布置的保护元件并联连接在具有PN结，肖特基结或电容器的受保护元件的两个端子之间 。 由于可以在彼此相邻的第一和第二n +区之间进行放电，所以可以在不增加寄生电容的情况下衰减到达FET工作区域的静电能量。

公开(公告)号：US08450805B2

公开(公告)日：2013-05-28

申请号：US11314178

申请日：2005-12-22

申请人： Tetsuro Asano ,  Mikito Sakakibara

发明人： Tetsuro Asano ,  Mikito Sakakibara

IPC分类号： H01L23/62

CPC分类号： H01L27/0605 ,  H01L27/0251

摘要： A high-resistance element is connected as a part of a control resistor between a control terminal pad and a protecting element, immediately near the control terminal pad. Thus, even if a high-frequency analog signal leaks to the control resistor, the leaked signal is attenuated by the high-resistance element. This substantially eliminates the possibility of the high-frequency analog signal transmitting to the control terminal pad. Accordingly, an increase in insertion loss can be suppressed.

摘要翻译： 高电阻元件作为控制端子焊盘和保护元件之间的控制电阻器的一部分紧邻控制端子焊盘连接。 因此，即使高频模拟信号泄漏到控制电阻器，泄漏的信号也被高电阻元件衰减。 这基本上消除了高频模拟信号传输到控制端子焊盘的可能性。 因此，可以抑制插入损耗的增加。

公开(公告)号：US06914280B2

公开(公告)日：2005-07-05

申请号：US10686788

申请日：2003-10-17

申请人： Tetsuro Asano ,  Mikito Sakakibara ,  Yoshibumi Nakajima ,  Hidetoshi Ishihara

发明人： Tetsuro Asano ,  Mikito Sakakibara ,  Yoshibumi Nakajima ,  Hidetoshi Ishihara

IPC分类号： H01L21/28 ,  H01L21/338 ,  H01L21/82 ,  H01L21/822 ,  H01L21/8252 ,  H01L27/02 ,  H01L27/04 ,  H01L27/06 ,  H01L27/088 ,  H01L29/41 ,  H01L29/47 ,  H01L29/812 ,  H01L29/872 ,  H03K17/08 ,  H03K17/693 ,  H01L29/80 ,  H01L23/34 ,  H01L29/40 ,  H01P1/00

CPC分类号： H01L21/8252 ,  H01L27/0255 ,  H01L27/0605 ,  H01L27/088

摘要： Since a 5 GHz-band broadband has a frequency twice that of 2.4 GHz, the parasitic capacitance greatly influences deterioration in isolation of a switching device used in this frequency region. Therefore, to improve isolation, a shunt FET is added to the device. The switching device also includes a protecting element that has a first n+-type region, an insulating region and a second n+-type region. This protecting element is connected in parallel between two electrodes of the shunt FET. Since electrostatic charges are discharged between the first and second n+-type regions, the electrostatic energy reaching an operation region of the shunt FET can be reduced without an increase in parasitic capacitance.

摘要翻译： 由于5 GHz频带宽带的频率是2.4 GHz的两倍，因此寄生电容极大地影响了该频率区域中使用的开关器件的隔离度的劣化。 因此，为了提高隔离度，在器件中添加了分流FET。 开关装置还包括具有第一n + + +型区域，绝缘区域和第二n + +型区域的保护元件。 该保护元件并联在并联FET的两个电极之间。 由于静电电荷在第一和第二n + + +型区域之间放电，所以可以减小到达分流FET的工作区域的静电能量，而不增加寄生电容。

公开(公告)号：US06682968B2

公开(公告)日：2004-01-27

申请号：US10205620

申请日：2002-07-26

申请人： Tetsuro Asano ,  Katsuaki Onoda ,  Yoshibumi Nakajima ,  Shigeyuki Murai ,  Hisaaki Tominaga ,  Koichi Hirata ,  Mikito Sakakibara ,  Hidetoshi Ishihara

发明人： Tetsuro Asano ,  Katsuaki Onoda ,  Yoshibumi Nakajima ,  Shigeyuki Murai ,  Hisaaki Tominaga ,  Koichi Hirata ,  Mikito Sakakibara ,  Hidetoshi Ishihara

IPC分类号： H01L218234

CPC分类号： H01L29/66143 ,  H01L29/872

摘要： A Schottky barrier diode has a Schottky electrode formed on an operation region of a GaAs substrate and an ohmic electrode surrounding the Schottky electrode. The ohmic electrode is disposed directly on an impurity-implanted region formed on the substrate. A nitride film insulates the ohmic electrode from a wiring layer connected to the Schottky electrode crossing over the ohmic electrode. The planar configuration of this device does not include the conventional polyimide layer, and thus has a better high frequency characteristics than conventional devices.

摘要翻译： 肖特基势垒二极管在GaAs衬底的工作区域和围绕肖特基电极的欧姆电极上形成肖特基电极。 欧姆电极直接设置在形成在基板上的杂质注入区域上。 氮化膜将欧姆电极与穿过欧姆电极的肖特基电极连接的布线层绝缘。 该器件的平面结构不包括传统的聚酰亚胺层，因此具有比常规器件更好的高频特性。

公开(公告)号：US20060151816A1

公开(公告)日：2006-07-13

申请号：US10521941

申请日：2002-11-28

申请人： Tetsuro Asano ,  Mikito Sakakibara ,  Toshikazu Hirai

发明人： Tetsuro Asano ,  Mikito Sakakibara ,  Toshikazu Hirai

IPC分类号： H01L29/80

CPC分类号： H01L29/812 ,  H01L27/0248 ,  H01L27/0255 ,  H01L29/808

摘要： A protecting element, comprising a first n+-type region, an insulating region, and a second n+-type region, is connected in parallel between two terminals of an FET. Since discharge across the first and second n+ regions is enabled, electrostatic energy that reaches the operating region of the FET can be attenuated without increasing the parasitic capacitance.

摘要翻译： 在FET的两个端子之间并联连接包括第一n +型区域，绝缘区域和第二n +型区域的保护元件。 由于能够使第一和第二n +区域的放电得以实现，所以到达FET工作区域的静电能量可以衰减而不增加寄生电容。

公开(公告)号：US20050121730A1

公开(公告)日：2005-06-09

申请号：US10505438

申请日：2003-09-08

申请人： Tetsuro Asano ,  Mikito Sakakibara ,  Toshikazu Hirai

发明人： Tetsuro Asano ,  Mikito Sakakibara ,  Toshikazu Hirai

IPC分类号： H01L27/02 ,  H01L29/80 ,  H01L29/812 ,  H01L29/861 ,  H01L29/76

CPC分类号： H01L27/0255 ,  H01L24/48 ,  H01L27/0248 ,  H01L27/0288 ,  H01L29/66098 ,  H01L29/80 ,  H01L29/812 ,  H01L29/861 ,  H01L2924/00014 ,  H01L2924/13055 ,  H01L2224/45099 ,  H01L2224/85399 ,  H01L2224/05599 ,  H01L2924/00

摘要： With a microwave FET, an incorporated Schottky junction capacitance or PN junction capacitance is small and such a junction is weak against static electricity. However, with a microwave device, the method of connecting a protecting diode cannot be used since this method increases the parasitic capacitance and causes degradation of the high-frequency characteristics. In order to solve the above problems, a protecting element, having a first n+-type region—insulating region—second n+-type region arrangement is connected in parallel between two terminals of a protected element having a PN junction, Schottky junction, or capacitor. Since discharge can be performed between the first and second n+ regions that are adjacent each other, electrostatic energy that would reach the operating region of an FET can be attenuated without increasing the parasitic capacitance.

摘要翻译： 使用微波FET，结合的肖特基结电容或PN结电容小，并且这种结对静电弱。 然而，利用微波装置，不能使用连接保护二极管的方法，因为这种方法增加了寄生电容并导致高频特性的劣化。 为了解决上述问题，具有第一n + + / - 型区域 - 绝缘区域 - 第二n + + - / - 域区域布置的保护元件并联在 受保护元件的两个端子具有PN结，肖特基结或电容器。 由于可以在彼此相邻的第一和第二正交区域之间进行放电，所以可以衰减到达FET操作区域的静电能量，而不增加寄生电容。

公开(公告)号：US06867115B2

公开(公告)日：2005-03-15

申请号：US10211311

申请日：2002-08-05

申请人： Tetsuro Asano ,  Toshikazu Hirai ,  Takayoshi Higashino ,  Koichi Hirata ,  Mikito Sakakibara

发明人： Tetsuro Asano ,  Toshikazu Hirai ,  Takayoshi Higashino ,  Koichi Hirata ,  Mikito Sakakibara

IPC分类号： H01L21/8252 ,  H01L27/06 ,  H01L21/265

CPC分类号： H01L24/05 ,  H01L21/8252 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L27/0605 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05556 ,  H01L2224/05644 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2224/48644 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01031 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/05042 ,  H01L2924/10329 ,  H01L2924/12032 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00

摘要： The conventional compound semiconductor switching device is prone to have a large chip size as the gate width needs to be large for achieving a low insertion loss and the separation between the connecting pad and the circuit wiring needs to be larger than 20 μm for obtaining a proper isolation between them. The overall chip size is reduced, first, by reducing the gate width of the switching FET operating at frequencies above 2.4 GHz to 700 μm or smaller together with the omission of the shunt FET, and, then, by reducing the separation between the connecting pad and the circuit wiring to 20 μm or smaller. This reduction of the separation is made possible by the introduction of an insulating film and a impurity region between the outermost portion of the connecting pad and the substrate for preventing the extension of the depletion layer. The manufacturing method of this device does not need any additional processing step for accommodating the above structure, and is capable of producing a device having a size of one fifth of the conventional device.

摘要翻译： 由于栅极宽度需要较大以达到低插入损耗，因此传统的化合物半导体开关器件容易具有大的芯片尺寸，并且连接焊盘和电路布线之间的间隔需要大于20μm以获得适当的 他们之间的隔离。 总体芯片尺寸减小，首先，通过减少在2.4GHz以上频率工作的开关FET的栅极宽度与省略分路FET一起减少到700μm或更小，然后通过减小连接焊盘之间的间隔 并且电路布线为20mum以下。 通过在连接焊盘的最外部分和衬底之间引入绝缘膜和杂质区域，可以实现分离的这种减少，以防止耗尽层的延伸。 该装置的制造方法不需要用于容纳上述结构的任何额外的处理步骤，并且能够制造具有常规装置的五分之一尺寸的装置。

公开(公告)号：US06853072B2

公开(公告)日：2005-02-08

申请号：US10414490

申请日：2003-04-16

申请人： Tetsuro Asano ,  Mikito Sakakibara

发明人： Tetsuro Asano ,  Mikito Sakakibara

IPC分类号： H01L23/482 ,  H01L23/552 ,  H01L23/66 ,  H01L29/417 ,  H01L23/34

CPC分类号： H01L23/66 ,  H01L23/4824 ,  H01L23/552 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L29/4175 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/05644 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48644 ,  H01L2224/48666 ,  H01L2224/48669 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01031 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/05042 ,  H01L2924/10161 ,  H01L2924/10329 ,  H01L2924/12032 ,  H01L2924/1306 ,  H01L2924/13063 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/16235 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012

摘要： Posts are disposed at the surroundings of an FET and a shield metal supported by the posts is placed above the FET to create a void between the FET and the shield metal. Since the separation between the FET and the shield metal is small, the resin does not enter the void. A resin layer cover the shield metal. The shield metal is connected to an electrode pad that receives a DC control signal. Although high frequency signals that are applied to the FET may leak between the source and drain electrodes of the FET through the resin layer covering the FET even when the FET is switched off, the void and the shield metal prevent such signal leakage.

摘要翻译： 端子设置在FET的周围，并且由FET支撑的屏蔽金属被放置在FET上方，以在FET和屏蔽金属之间产生空隙。 由于FET和屏蔽金属之间的间隔小，树脂不会进入空隙。 树脂层覆盖屏蔽金属。 屏蔽金属连接到接收DC控制信号的电极焊盘。 虽然施加到FET的高频信号也可能通过覆盖FET的树脂层在FET的源极和漏极之间泄漏，即使FET被关闭，空隙和屏蔽金属也防止这种信号泄漏。