公开(公告)号：US20170338351A1

公开(公告)日：2017-11-23

申请号：US15191542

申请日：2016-06-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： ZHIBIAO ZHOU ,  Ding-Lung Chen ,  Chen-Bin Lin ,  SANPO WANG ,  Chung-Yuan Lee ,  Chi-Fa Ku

IPC: H01L29/786 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L29/78609 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/792

Abstract: A semiconductor device is provided in the present invention, which includes a substrate, an oxide-semiconductor layer, source/drain regions, a dielectric layer, a first gate electrode, a second gate electrode and a charge storage structure. The oxide-semiconductor layer is disposed on the first gate electrode on the substrate. The source/drain regions are disposed on the oxide-semiconductor layer. The first dielectric layer covers on the oxide-semiconductor layer and source/drain regions. A second gate electrode is disposed between source/drain regions and partially covers the oxide-semiconductor layer. The oxide-semiconductor layer may be optionally disposed between the first gate electrode and the oxide-semiconductor layer or be disposed on the second gate electrode.

公开(公告)号：US20170110192A1

公开(公告)日：2017-04-20

申请号：US15382755

申请日：2016-12-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： ZHIBIAO ZHOU ,  Chen-Bin Lin ,  Chi-Fa Ku ,  Shao-Hui Wu

IPC: G11C14/00 ,  H01L49/02 ,  H01L29/04 ,  H01L27/105 ,  H01L29/24 ,  H01L29/66 ,  H01L27/108

CPC classification number: G11C14/0009 ,  G11C14/0027 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02194 ,  H01L27/10808 ,  H01L27/1085 ,  H01L27/1225 ,  H01L27/1255 ,  H01L27/1259 ,  H01L28/60

Abstract: A method for fabricating a semiconductor memory device is disclosed. A semiconductor substrate having a main surface is prepared. At least a first dielectric layer is formed on the main surface of the semiconductor substrate. A first OS FET device and a second OS FET device are formed on the first dielectric layer. At least a second dielectric layer is formed to cover the first dielectric layer, the first OS FET device, and the second OS FET device. A first MIM capacitor and a second MIM capacitor are formed on the second dielectric layer. The first MIM capacitor is electrically coupled to the first OS FET device, thereby constituting a DOSRAM cell. The second MIM capacitor is electrically coupled to the second OS FET device, thereby constituting a NOSRAM cell.

公开(公告)号：US20170098599A1

公开(公告)日：2017-04-06

申请号：US14873189

申请日：2015-10-01

Applicant: United Microelectronics Corp.

Inventor： ZHIBIAO ZHOU ,  Shao-Hui Wu ,  Chi-Fa Ku ,  Chen-Bin Lin

IPC: H01L23/498 ,  H01L27/108 ,  H01L27/115 ,  H01L29/66 ,  H01L27/12 ,  H01L21/48 ,  H01L29/786

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L23/147 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5223 ,  H01L23/5385 ,  H01L27/1218 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1255 ,  H01L27/1259 ,  H01L27/1262 ,  H01L29/66969 ,  H01L29/7869 ,  H01L2224/16225 ,  H01L2924/15311

Abstract: A manufacturing method of an oxide semiconductor device includes the following steps. An interposer substrate is provided. At least one oxide semiconductor transistor is formed on the interposer substrate. At least one trough silicon via (TSV) is formed in the interposer substrate. An interconnection structure on the interposer substrate, and the at least one oxide semiconductor transistor is connected to the interconnection structure.

公开(公告)号：US09564217B1

公开(公告)日：2017-02-07

申请号：US14886116

申请日：2015-10-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhibiao Zhou ,  Chen-Bin Lin ,  Chi-Fa Ku ,  Shao-Hui Wu

IPC: H01L27/10 ,  H01L29/04 ,  H01L29/24 ,  H01L29/66 ,  H01L29/78 ,  G11C14/00 ,  H01L29/786 ,  H01L27/108 ,  H01L27/105

CPC classification number: G11C14/0009 ,  G11C14/0027 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02194 ,  H01L27/10808 ,  H01L27/1085 ,  H01L27/1225 ,  H01L27/1255 ,  H01L27/1259 ,  H01L28/60

Abstract: A semiconductor memory device includes a semiconductor substrate having a main surface, at least a first dielectric layer on the main surface of the semiconductor substrate, a first OS FET device and a second OS FET device disposed on the first dielectric layer, at least a second dielectric layer covering the first dielectric layer, the first OS FET device, and the second OS FET device, a first MIM capacitor on the second dielectric layer and electrically coupled to the first OS FET device, and a second MIM capacitor on the second dielectric layer and electrically coupled to the second OS FET device.

Abstract translation: 半导体存储器件包括具有主表面的半导体衬底，在半导体衬底的主表面上的至少第一电介质层，设置在第一介电层上的第一OS FET器件和第二OS FET器件，至少第二 覆盖第一电介质层的介质层，第一OS FET器件和第二OS FET器件，第二介电层上的第一MIM电容器，并且电耦合到第一OS FET器件;以及第二MIM电容器， 并电耦合到第二OS FET器件。

公开(公告)号：US10043917B2

公开(公告)日：2018-08-07

申请号：US15059311

申请日：2016-03-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhibiao Zhou ,  Shao-Hui Wu ,  Chen-Bin Lin ,  Ding-Lung Chen ,  Chi-Fa Ku

IPC: H01L21/00 ,  H01L29/786 ,  H01L29/66 ,  H01L21/426

Abstract: An oxide semiconductor device and a method for manufacturing the same are provided in the present invention. The oxide semiconductor device includes a back gate, an oxide semiconductor film, a pair of source and drain electrodes, agate insulating film, a gate electrode on the oxide semiconductor film with the gate insulating film therebetween, an insulating layer covering only over the gate electrode and the pair of source and drain electrodes, and a top blocking film over the insulating layer.

公开(公告)号：US09893066B2

公开(公告)日：2018-02-13

申请号：US15432165

申请日：2017-02-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhi-Biao Zhou ,  Shao-Hui Wu ,  Chi-Fa Ku ,  Chen-Bin Lin ,  Su Xing ,  Tien-Yu Hsieh

IPC: H01L29/49 ,  H01L27/105 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L27/1052 ,  H01L27/108 ,  H01L27/115 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L28/40 ,  H01L29/66742 ,  H01L29/7869

Abstract: A semiconductor transistor device includes an oxide semiconductor layer having an active surface, a source electrode, a drain electrode, a gate electrode and a control capacitor. The gate electrode, the source electrode and the drain electrode are directly in contact with the active surface. The gate electrode is disposed between the drain electrode and the source electrode. The gate electrode, the source electrode and the drain electrode are separated from each other. The control capacitor is electrically connected to the gate electrode through a connection.

公开(公告)号：US09749567B2

公开(公告)日：2017-08-29

申请号：US14953411

申请日：2015-11-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhibiao Zhou ,  Chen-Bin Lin ,  Ding-Lung Chen

IPC: H04N5/374 ,  H01L31/0352 ,  H01L27/146 ,  H04N9/04

CPC classification number: H04N5/374 ,  H01L27/14667 ,  H01L31/035218 ,  H04N5/3745 ,  H04N9/04

Abstract: An operating method of an image sensor includes the following steps. The image sensor includes at least one pixel unit. The pixel unit includes a photoelectric conversion unit, a first control unit, a capacitor unit, and a sensing unit. The photoelectric conversion unit includes a quantum film photoelectric conversion unit, and the first control unit includes an oxide semiconductor transistor. The capacitor unit is coupled to the first control unit, and the sensing unit is configured to sense signals at a sense point coupled between the first control unit and the sensing unit. The pixel unit is discharged before a readout operation. The capacitor unit is charged by electrons emitted from the photoelectric conversion unit when the photoelectric conversion unit is excited by light. Signals at the sense point are then sensed by the sensing unit.

公开(公告)号：US20170170257A1

公开(公告)日：2017-06-15

申请号：US15352551

申请日：2016-11-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： ZHIBIAO ZHOU ,  Shao-Hui Wu ,  Chi-Fa Ku ,  Chen-Bin Lin

IPC: H01L49/02

CPC classification number: H01L28/91 ,  H01L28/92

Abstract: A capacitor includes: a bottom electrode; a middle electrode on the bottom electrode; a top electrode on the middle electrode; a first dielectric layer between the bottom electrode and the middle electrode; and a second dielectric layer between the middle electrode and the top electrode. Preferably, the second dielectric layer is disposed on at least a sidewall of the middle electrode to physically contact the first dielectrically, and the middle electrode includes a H-shape.

公开(公告)号：US20170125599A1

公开(公告)日：2017-05-04

申请号：US14960041

申请日：2015-12-04

Applicant: United Microelectronics Corp.

Inventor： Hai-Biao Yao ,  Shao-Hui Wu ,  Chi-Fa Ku ,  Chen-Bin Lin ,  Zhi-Biao Zhou

IPC: H01L29/786 ,  H01L29/51 ,  H01L21/033 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/7869 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02565 ,  H01L21/0332 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66795 ,  H01L29/66969 ,  H01L29/785 ,  H01L29/78606 ,  H01L29/78696

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes an oxide semiconductor protrusion, a source, a drain, an oxide semiconductor layer, a first O-barrier layer, a gate electrode, a second O-barrier layer, and an H-barrier layer. The oxide semiconductor protrusion is disposed on an oxide substrate. The source and the drain are respectively disposed on opposite ends of the oxide semiconductor protrusion. The oxide semiconductor layer is disposed on the oxide substrate and covers the oxide semiconductor protrusion, the source, and the drain. The first O-barrier layer is disposed on the oxide semiconductor layer. The gate electrode is disposed on the first O-barrier layer and across the oxide semiconductor protrusion. The second O-barrier layer is disposed on the gate electrode. The H-barrier layer is disposed on the oxide substrate and covers the second O-barrier layer.

公开(公告)号：US09627549B1

公开(公告)日：2017-04-18

申请号：US14874546

申请日：2015-10-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhi-Biao Zhou ,  Shao-Hui Wu ,  Chi-Fa Ku ,  Chen-Bin Lin ,  Su Xing ,  Tien-Yu Hsieh

IPC: H01L29/49 ,  H01L29/786 ,  H01L29/66 ,  H01L49/02 ,  H01L27/115 ,  H01L27/108

CPC classification number: H01L27/1052 ,  H01L27/108 ,  H01L27/115 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L28/40 ,  H01L29/66742 ,  H01L29/7869

Abstract: A semiconductor transistor device includes an oxide semiconductor layer having an active surface, a source electrode, a drain electrode, a gate electrode and a control capacitor. The gate electrode, the source electrode and the drain electrode are directly in contact with the active surface. The gate electrode is disposed between the drain electrode and the source electrode. The gate electrode, the source electrode and the drain electrode are separated from each other. The control capacitor is electrically connected to the gate electrode through a connection.