公开(公告)号：US09564217B1

公开(公告)日：2017-02-07

申请号：US14886116

申请日：2015-10-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhibiao Zhou ,  Chen-Bin Lin ,  Chi-Fa Ku ,  Shao-Hui Wu

IPC: H01L27/10 ,  H01L29/04 ,  H01L29/24 ,  H01L29/66 ,  H01L29/78 ,  G11C14/00 ,  H01L29/786 ,  H01L27/108 ,  H01L27/105

CPC classification number: G11C14/0009 ,  G11C14/0027 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02194 ,  H01L27/10808 ,  H01L27/1085 ,  H01L27/1225 ,  H01L27/1255 ,  H01L27/1259 ,  H01L28/60

Abstract: A semiconductor memory device includes a semiconductor substrate having a main surface, at least a first dielectric layer on the main surface of the semiconductor substrate, a first OS FET device and a second OS FET device disposed on the first dielectric layer, at least a second dielectric layer covering the first dielectric layer, the first OS FET device, and the second OS FET device, a first MIM capacitor on the second dielectric layer and electrically coupled to the first OS FET device, and a second MIM capacitor on the second dielectric layer and electrically coupled to the second OS FET device.

Abstract translation: 半导体存储器件包括具有主表面的半导体衬底，在半导体衬底的主表面上的至少第一电介质层，设置在第一介电层上的第一OS FET器件和第二OS FET器件，至少第二 覆盖第一电介质层的介质层，第一OS FET器件和第二OS FET器件，第二介电层上的第一MIM电容器，并且电耦合到第一OS FET器件;以及第二MIM电容器， 并电耦合到第二OS FET器件。

公开(公告)号：US20160322502A1

公开(公告)日：2016-11-03

申请号：US14724799

申请日：2015-05-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： ZHIBIAO ZHOU ,  Shao-Hui Wu ,  Chi-Fa Ku

IPC: H01L29/786 ,  H01L29/51 ,  H01L29/49 ,  H01L29/24 ,  H01L29/04

CPC classification number: H01L29/7869 ,  H01L27/1218 ,  H01L27/1225 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/24 ,  H01L29/4908 ,  H01L29/4916 ,  H01L29/517 ,  H01L29/66969 ,  H01L29/78603

Abstract: A semiconductor structure includes a substrate and a first element disposed in the substrate and arranged along a first direction. The first element is made of a semiconductor oxide material. The semiconductor structure also includes a dielectric layer disposed on the first element, and a second element, disposed on the dielectric layer and arranged along the first direction. The second element is used as a gate of a transistor structure.

Abstract translation: 半导体结构包括基板和设置在基板中并沿着第一方向布置的第一元件。 第一元件由半导体氧化物材料制成。 半导体结构还包括设置在第一元件上的电介质层和设置在电介质层上并沿着第一方向布置的第二元件。 第二个元件用作晶体管结构的栅极。

公开(公告)号：US20160163693A1

公开(公告)日：2016-06-09

申请号：US14588991

申请日：2015-01-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： ZHIBIAO ZHOU ,  Shao-Hui Wu ,  Chi-Fa Ku

IPC: H01L27/06 ,  H01L49/02

CPC classification number: H01L28/60 ,  H01L28/10 ,  H01L28/87 ,  H01L28/91

Abstract: A structure with an inductor and a MIM capacitor is provided. The structure includes a dielectric layer, an inductor and a MIM capacitor. The inductor and the MIM capacitor are disposed within the dielectric layer. The inductor includes a core and a wire surrounding the core. The MIM capacitor includes a top electrode, a bottom electrode and an insulating layer. The top electrode or the bottom electrode includes a material which forms the core.

Abstract translation: 提供具有电感器和MIM电容器的结构。 该结构包括电介质层，电感器和MIM电容器。 电感器和MIM电容器设置在电介质层内。 电感器包括芯和围绕芯的导线。 MIM电容器包括顶电极，底电极和绝缘层。 顶部电极或底部电极包括形成芯的材料。

公开(公告)号：US10115786B2

公开(公告)日：2018-10-30

申请号：US15352551

申请日：2016-11-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhibiao Zhou ,  Shao-Hui Wu ,  Chi-Fa Ku ,  Chen-Bin Lin

IPC: H01L49/02 ,  H01G11/24

Abstract: A capacitor includes: a bottom electrode; a middle electrode on the bottom electrode; a top electrode on the middle electrode; a first dielectric layer between the bottom electrode and the middle electrode; and a second dielectric layer between the middle electrode and the top electrode. Preferably, the second dielectric layer is disposed on at least a sidewall of the middle electrode to physically contact the first dielectrically, and the middle electrode includes a H-shape.

公开(公告)号：US10056493B2

公开(公告)日：2018-08-21

申请号：US15853875

申请日：2017-12-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhibiao Zhou ,  Ding-Lung Chen ,  Chen-Bin Lin ,  Sanpo Wang ,  Chung-Yuan Lee ,  Chi-Fa Ku

IPC: H01L29/78 ,  H01L29/786 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L29/78609 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/792

Abstract: A semiconductor device is provided in the present invention, which includes a substrate, an oxide-semiconductor layer, source/drain regions, a first dielectric layer covering on the oxide-semiconductor layer and the source/drain regions, a second gate between the two source/drain regions and partially covering the oxide-semiconductor layer, and a charge storage structure between the first gate electrode and the oxide-semiconductor layer.

公开(公告)号：US20170179295A1

公开(公告)日：2017-06-22

申请号：US15447081

申请日：2017-03-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： ZHIBIAO ZHOU ,  Shao-Hui Wu ,  Chi-Fa Ku

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/49 ,  H01L29/51 ,  H01L29/04 ,  H01L29/24

CPC classification number: H01L29/7869 ,  H01L27/1218 ,  H01L27/1225 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/24 ,  H01L29/4908 ,  H01L29/4916 ,  H01L29/517 ,  H01L29/66969 ,  H01L29/78603

Abstract: A semiconductor structure includes a substrate and a first element disposed in the substrate and arranged along a first direction. The first element is made of a semiconductor oxide material. The semiconductor structure also includes a dielectric layer disposed on the first element, and a second element, disposed on the dielectric layer and arranged along the first direction. The second element is used as a gate of a transistor structure.

公开(公告)号：US20170098712A1

公开(公告)日：2017-04-06

申请号：US14874546

申请日：2015-10-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhi-Biao Zhou ,  Shao-Hui Wu ,  Chi-Fa Ku ,  Chen-Bin Lin ,  Su Xing ,  Tien-Yu Hsieh

IPC: H01L29/786 ,  H01L27/108 ,  H01L27/115 ,  H01L29/66 ,  H01L49/02

CPC classification number: H01L27/1052 ,  H01L27/108 ,  H01L27/115 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L28/40 ,  H01L29/66742 ,  H01L29/7869

Abstract: A semiconductor transistor device includes an oxide semiconductor layer having an active surface, a source electrode, a drain electrode, a gate electrode and a control capacitor. The gate electrode, the source electrode and the drain electrode are directly in contact with the active surface. The gate electrode is disposed between the drain electrode and the source electrode. The gate electrode, the source electrode and the drain electrode are separated from each other. The control capacitor is electrically connected to the gate electrode through a connection.

公开(公告)号：US09607123B2

公开(公告)日：2017-03-28

申请号：US14598236

申请日：2015-01-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Xing Hua Zhang ,  Chi-Fa Ku ,  Hong Liao ,  Ye Chao Li ,  Hui Yang

IPC: G06F17/50 ,  H01L23/58 ,  H01L21/66 ,  H01L23/528 ,  H01L21/8238 ,  H01L27/02 ,  H01L23/10 ,  H01L27/06 ,  H01L23/00

CPC classification number: G06F17/5081 ,  H01L21/823871 ,  H01L22/34 ,  H01L23/10 ,  H01L23/528 ,  H01L23/562 ,  H01L23/58 ,  H01L27/0266 ,  H01L27/0629 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor monitoring device includes a substrate, a die seal ring formed on the substrate, a deep n-typed well formed in the substrate under the die seal ring, and a monitoring device electrically connected to the die seal ring. The monitoring device is formed in a scribe line region defined on the substrate. A width of the deep n-typed well is larger than a width of the die seal ring.

公开(公告)号：US20170084614A1

公开(公告)日：2017-03-23

申请号：US14856565

申请日：2015-09-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shao-Hui Wu ,  ZHIBIAO ZHOU ,  HAI BIAO YAO ,  Chi-Fa Ku ,  Chen-Bin Lin

IPC: H01L27/108 ,  H01L29/786

CPC classification number: H01L27/10832 ,  H01L27/10867 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/7869

Abstract: A memory cell includes a substrate, a deep trench (DT) capacitor formed in the substrate, at least an insulting layer formed on the substrate, and an oxide semiconductor field effect transistor (OS FET) device formed on the insulating layer. And more important, the OS FET device is electrically connected to the DT capacitor.

公开(公告)号：US09530834B1

公开(公告)日：2016-12-27

申请号：US14967344

申请日：2015-12-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhibiao Zhou ,  Shao-Hui Wu ,  Chi-Fa Ku ,  Chen-Bin Lin

IPC: H01L29/94 ,  H01L49/02

CPC classification number: H01L28/91 ,  H01L28/92

Abstract: A method for fabricating capacitor is disclosed. The method includes the steps of: providing a material layer; forming a patterned first conductive layer on the material layer, forming a first dielectric layer on the patterned first conductive layer; forming a second conductive layer and a cap layer on the first dielectric layer; removing part of the cap layer to form a spacer on the second conductive layer; and using the spacer to remove part of the second conductive layer for forming a trench above the patterned first conductive layer and fin-shaped structures adjacent to the trench.

Abstract translation: 公开了制造电容器的方法。 该方法包括以下步骤：提供材料层; 在所述材料层上形成图案化的第一导电层，在所述图案化的第一导电层上形成第一介电层; 在所述第一介电层上形成第二导电层和盖层; 去除所述盖层的一部分以在所述第二导电层上形成间隔物; 以及使用间隔件去除用于在图案化的第一导电层上方形成沟槽的第二导电层的一部分和与沟槽相邻的鳍状结构。