公开(公告)号：US20200185505A1

公开(公告)日：2020-06-11

申请号：US16792308

申请日：2020-02-17

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chia-Wei Wu ,  Ting-Pang Chung ,  Tien-Chen Chan ,  Shu-Yen Chan

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L21/02 ,  H01L29/49 ,  H01L27/12 ,  H01L27/108

Abstract: A semiconductor device includes a substrate having at least a trench formed therein. A conductive material fills a lower portion of the trench. A barrier layer is between the conductive material and the substrate. An insulating layer is in the trench and completely covers the conductive material and the barrier layer, wherein a portion of the insulating layer covering the barrier layer has a bird's peak profile.

公开(公告)号：US20190035792A1

公开(公告)日：2019-01-31

申请号：US15876216

申请日：2018-01-22

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Tsuo-Wen Lu ,  Ger-Pin Lin ,  Tien-Chen Chan ,  Shu-Yen Chan

IPC: H01L27/108 ,  H01L29/423 ,  H01L29/51 ,  H01L29/49 ,  H01L21/02 ,  H01L21/28

CPC classification number: H01L27/10823 ,  H01L21/02164 ,  H01L21/0228 ,  H01L21/28088 ,  H01L21/28194 ,  H01L21/28211 ,  H01L27/10876 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/66621

Abstract: A semiconductor device includes a semiconductor substrate having a gate trench including an upper trench and a lower trench. The upper trench is wider than the lower trench. A gate is embedded in the gate trench. The gate includes an upper portion and a lower portion. A first gate dielectric layer is between the upper portion and a sidewall of the upper trench. The first gate dielectric layer has a first thickness. A second gate dielectric layer is between the lower portion and a sidewall of the lower trench and between the lower portion and a bottom surface of the lower trench. The second gate dielectric layer has a second thickness that is smaller than the first thickness.

公开(公告)号：US10056388B2

公开(公告)日：2018-08-21

申请号：US15465622

申请日：2017-03-22

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ger-Pin Lin ,  Yung-Ming Wang ,  Tien-Chen Chan ,  Shu-Yen Chan

IPC: H01L29/423 ,  H01L27/108 ,  H01L21/265 ,  H01L29/10 ,  H01L29/49 ,  H01L21/762 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/10876 ,  H01L21/76237 ,  H01L27/10823 ,  H01L29/1037 ,  H01L29/1041 ,  H01L29/105 ,  H01L29/4236 ,  H01L29/495 ,  H01L29/66621 ,  H01L29/78 ,  H01L29/7834

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a memory region defined thereon; forming a trench in the substrate; performing a first ion implantation process to form a first doped region having a first conductive type in the substrate adjacent to the trench; forming a gate electrode in the trench; and performing a second ion implantation process to form a second doped region having a second conductive type in the substrate above the gate electrode.

公开(公告)号：US20180190660A1

公开(公告)日：2018-07-05

申请号：US15465622

申请日：2017-03-22

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ger-Pin Lin ,  Yung-Ming Wang ,  Tien-Chen Chan ,  Shu-Yen Chan

IPC: H01L27/108 ,  H01L21/265 ,  H01L29/423 ,  H01L29/10 ,  H01L29/49 ,  H01L21/762

CPC classification number: H01L27/10876 ,  H01L21/26513 ,  H01L21/76237 ,  H01L27/10823 ,  H01L29/1037 ,  H01L29/1041 ,  H01L29/105 ,  H01L29/4236 ,  H01L29/495 ,  H01L29/66621 ,  H01L29/78 ,  H01L29/7834

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a memory region defined thereon; forming a trench in the substrate; performing a first ion implantation process to form a first doped region having a first conductive type in the substrate adjacent to the trench; forming a gate electrode in the trench; and performing a second ion implantation process to form a second doped region having a second conductive type in the substrate above the gate electrode.

公开(公告)号：US09966468B2

公开(公告)日：2018-05-08

申请号：US15214429

申请日：2016-07-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tien-Chen Chan ,  Yi-Fan Li ,  Li-Wei Feng ,  Ming-Hua Chang ,  Yu-Shu Lin ,  Shu-Yen Chan

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/06

CPC classification number: H01L29/7851 ,  H01L21/02164 ,  H01L21/0217 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for fabricating semiconductor device is disclosed. First, a fin-shaped structure is formed on a substrate, a first liner is formed on the substrate and the fin-shaped structure, a second liner is formed on the first liner, part of the second liner and part of the first liner are removed to expose a top surface of the fin-shaped structure, part of the first liner between the fin-shaped structure and the second liner is removed to form a recess, and an epitaxial layer is formed in the recess.

公开(公告)号：US09899498B2

公开(公告)日：2018-02-20

申请号：US15590510

申请日：2017-05-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tien-Chen Chan ,  Yi-Fan Li ,  Yen-Hsing Chen ,  Chun-Yu Chen ,  Chung-Ting Huang ,  Zih-Hsuan Huang ,  Ming-Hua Chang ,  Yu-Shu Lin ,  Shu-Yen Chan

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/0262 ,  H01L29/1054 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device is provided, including a substrate with an isolation layer formed thereon, wherein the substrate has a fin protruding up through the isolation layer to form a top surface and a pair of lateral sidewalls of the fin above the isolation layer; a silicon-germanium (SiGe) layer epitaxially grown on the top surface and the lateral sidewalls of the fin; and a gate stack formed on the isolation layer and across the fin, wherein the fin and the gate stack respectively extend along a first direction and a second direction. The SiGe layer formed on the top surface has a first thickness, the SiGe layer formed on said lateral sidewall has a second thickness, and a ratio of the first thickness to the second thickness is in a range of 1:10 to 1:30.

公开(公告)号：US09673324B1

公开(公告)日：2017-06-06

申请号：US15246522

申请日：2016-08-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tien-I Wu ,  I-Cheng Hu ,  Yu-Shu Lin ,  Shu-Yen Chan ,  Neng-Hui Yang

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7846 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7853

Abstract: The present invention provides a metal oxide semiconductor (MOS) device, including a substrate, a gate structure on the substrate and a source/drain region disposed in the substrate at one side of the gate structure and in at least a part of an epitaxial structure, wherein the epitaxial structure includes a first buffer layer, which is an un-doped buffer layer, including a bottom portion disposed on a bottom surface of the epitaxial structure and a sidewall portion disposed on a concave sidewall of the epitaxial structure, an epitaxial layer which is encompassed by the first buffer layer, and a semiconductor layer which is disposed between the first buffer layer and the epitaxial layer. The source/drain region is disposed in the epitaxial structure.

公开(公告)号：US20170133460A1

公开(公告)日：2017-05-11

申请号：US14936651

申请日：2015-11-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tien-I Wu ,  I-cheng Hu ,  Yu-Shu Lin ,  Chun-Jen Chen ,  Tsung-Mu Yang ,  Kun-Hsin Chen ,  Neng-Hui Yang ,  Shu-Yen Chan

IPC: H01L29/06 ,  H01L21/3065 ,  H01L29/16 ,  H01L21/283 ,  H01L29/423 ,  H01L21/306 ,  H01L21/225

CPC classification number: H01L21/283 ,  H01L21/26506 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/3065 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: The present invention provides a method for forming a semiconductor structure, including: first, a substrate is provided. Next, at least two gate structures are formed on the substrate, each gate structure including two spacers disposed on two sides of the gate structure. Afterwards, a dry etching process is performed to remove parts of the substrate, so as to form a recess in the substrate, and a wet etching process is performed, to etch partial sidewalls of the recess, so as to form at least two tips on two sides of the recess respectively. In addition, parts of the spacer are also removed through the wet etching process, and each spacer includes a rounding corner disposed on a bottom surface of the spacer.

公开(公告)号：US08853740B2

公开(公告)日：2014-10-07

申请号：US13905148

申请日：2013-05-30

Applicant: United Microelectronics Corp.

Inventor： Chan-Lon Yang ,  Ted Ming-Lang Guo ,  Chin-I Liao ,  Chin-Cheng Chien ,  Shu-Yen Chan ,  Chun-Yuan Wu

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/324 ,  H01L21/8234 ,  H01L21/306

CPC classification number: H01L29/7848 ,  H01L21/30608 ,  H01L21/3247 ,  H01L21/823425 ,  H01L29/6656 ,  H01L29/66636

Abstract: A strained silicon channel semiconductor structure comprises a substrate having an upper surface, a gate structure formed on the upper surface, at least one recess formed in the substrate at lateral sides of the gate structure, wherein the recess has at least one sidewall which has an upper sidewall and a lower sidewall concaved in the direction to the gate structure, and the included angle between the upper sidewall and horizontal plane ranges between 54.5°-90°, and an epitaxial layer filled into the two recesses.

Abstract translation: 应变硅沟道半导体结构包括具有上表面的衬底，形成在上表面上的栅极结构，在栅极结构的侧面处形成在衬底中的至少一个凹部，其中凹部具有至少一个侧壁，其具有 上侧壁和下侧壁在与栅极结构的方向上凹陷，并且上侧壁和水平面之间的夹角在54.5°-90°之间，并且填充到两个凹部中的外延层。

公开(公告)号：US20130122691A1

公开(公告)日：2013-05-16

申请号：US13707613

申请日：2012-12-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chin-I Liao ,  Ching-I Li ,  Shu-Yen Chan

IPC: H01L21/20

CPC classification number: H01L21/20 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

Abstract: A method for forming a semiconductor structure is provided. First, multiple recesses are formed in a substrate. Second, a precursor mixture is provided to form a non-doped epitaxial layer on the inner surface of the recesses. The precursor mixture includes a silicon precursor, an epitaxial material precursor and a hydrogen-halogen compound. The flow rate ratio of the silicon precursor to the epitaxial material precursor is greater than 1.7. Later, a doped epitaxial layer including Si, the epitaxial material and the dopant is formed and substantially fills up the recess.

Abstract translation: 提供一种形成半导体结构的方法。 首先，在基板上形成多个凹部。 第二，提供前体混合物以在凹槽的内表面上形成非掺杂外延层。 前体混合物包括硅前体，外延材料前体和氢卤素化合物。 硅前体与外延材料前体的流速比大于1.7。 之后，形成包括Si，外延材料和掺杂剂的掺杂外延层，并基本上填充凹槽。