公开(公告)号：US20120241712A1

公开(公告)日：2012-09-27

申请号：US13254570

申请日：2011-04-12

申请人： Yimao Cai ,  Ru Huang ,  Yangyuan Wang ,  Yinglong Huang

发明人： Yimao Cai ,  Ru Huang ,  Yangyuan Wang ,  Yinglong Huang

IPC分类号： H01L45/00 ,  H01L21/62

CPC分类号： H01L45/1233 ,  H01L27/2472 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1273 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16

摘要： The present invention discloses a resistive-switching memory and the fabrication method thereof. The resistive-switching memory comprises a substrate, a top electrode, a bottom electrode, and a resistive-switching material interposed between the top and bottom electrodes, wherein the central portion of the bottom electrode protrudes upwards to form a peak shape, and the top electrode is in a plate shape. The peak structure of the bottom electrode reduces power consumption of the device. The fabrication method thereof comprises forming peak structures on the surface of the substrate by means of corrosion, and then growing bottom electrodes thereon to form bottom electrodes having peak shapes, and depositing resistive-switching material and top electrodes. The entire fabrication process is simple, and high integration degree of the device can be achieved.

摘要翻译： 本发明公开了一种电阻式开关存储器及其制造方法。 电阻开关存储器包括插入在顶部和底部电极之间的衬底，顶部电极，底部电极和电阻开关材料，其中底部电极的中心部分向上突出以形成峰形，顶部 电极为板状。 底部电极的峰值结构降低了器件的功耗。 其制造方法包括通过腐蚀在基板的表面上形成峰值结构，然后在其上生长底部电极，以形成具有峰形的底部电极，以及沉积电阻式切换材料和顶部电极。 整个制造工艺简单，可以实现高集成度的装置。

公开(公告)号：US20120168770A1

公开(公告)日：2012-07-05

申请号：US13391270

申请日：2011-11-18

申请人： Ru Huang ,  Xin Huang ,  Tianwei Zhang ,  Qianqian Huang ,  Shiqiang Qin

发明人： Ru Huang ,  Xin Huang ,  Tianwei Zhang ,  Qianqian Huang ,  Shiqiang Qin

IPC分类号： H01L29/20 ,  H01L29/12

CPC分类号： H01L23/38 ,  H01L23/3738 ,  H01L2924/0002 ,  H01L2924/00

摘要： A heat dissipation structure of a chip in the field of microelectronics is provided. The heat dissipation structure includes a P-type superlattice layer and an N-type superlattice layer formed over an upper surface of the chip by oxidation isolation. The P-type superlattice and the N-type superlattice are isolated by silicon oxide. Through a contact hole the P-type superlattice is electrically connected to a metal layer that is applied with a low potential in the chip, and a metal layer to be connected with an external power source is formed over the P-type superlattice. Through a contact hole the N-type superlattice is electrically connected to a metal layer that is applied with a high-potential power source in the chip, and a metal layer to be connected with an external power source is formed over the N-type superlattice. The potential of the external power source connected with the P-type superlattice is lower than that of the external power source connected with the N-type superlattice. The present invention can achieve heat dissipation of the chip and meanwhile prevent the ambient heat from transferring into the chip, by using the feature that the superlattice has a low thermal conductivity and phonon-localization-like behavior.

摘要翻译： 提供了微电子领域的芯片的散热结构。 散热结构包括通过氧化隔离在芯片的上表面上形成的P型超晶格层和N型超晶格层。 P型超晶格和N型超晶格被氧化硅隔离。 通过接触孔，P型超晶格与在芯片中施加低电位的金属层电连接，并且在P型超晶格上形成与外部电源连接的金属层。 通过接触孔，N型超晶格电连接到在芯片中施加高电位电源的金属层，并且在N型超晶格上形成与外部电源连接的金属层 。 与P型超晶格连接的外部电源的电位低于与N型超晶格连接的外部电源的电位。 本发明可以实现芯片的散热，同时通过使用超晶格具有低导热性和声子定位的特性的特征，同时防止环境热量转移到芯片中。

公开(公告)号：US08921174B2

公开(公告)日：2014-12-30

申请号：US13884095

申请日：2012-06-14

申请人： Ru Huang ,  Qianqian Huang ,  Zhan Zhan ,  Yingxin Qiu ,  Yangyuan Wang

发明人： Ru Huang ,  Qianqian Huang ,  Zhan Zhan ,  Yingxin Qiu ,  Yangyuan Wang

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/739

CPC分类号： H01L21/823892 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66356 ,  H01L29/7391

摘要： Disclosed herein is a method for fabricating a complementary tunneling field effect transistor based on a standard CMOS IC process, which belongs to the field of logic devices and circuits of field effect transistors in ultra large scaled integrated (ULSI) circuits. In the method, an intrinsic channel and body region of a TFET are formed by means of complementary P-well and N-well masks in the standard CMOS IC process to form a well doping, a channel doping and a threshold adjustment by implantation. Further, a bipolar effect in the TFET can be inhibited via a distance between a gate and a drain on a layout so that a complementary TFET is formed. In the method according to the invention, the complementary tunneling field effect transistor (TFET) can be fabricated by virtue of existing processes in the standard CMOS IC process without any additional masks and process steps.

摘要翻译： 本文公开了一种用于制造基于标准CMOS IC工艺的互补隧道场效应晶体管的方法，其属于超大规模集成（ULSI）电路中的场效应晶体管的逻辑器件和电路领域。 在该方法中，TFET的本征通道和体区通过在标准CMOS IC工艺中的互补P阱和N阱掩模形成，以形成阱掺杂，沟道掺杂和通过注入进行阈值调整。 此外，可以通过布局上的栅极和漏极之间的距离来抑制TFET中的双极效应，从而形成互补的TFET。 在根据本发明的方法中，互补隧穿场效应晶体管（TFET）可以通过标准CMOS IC工艺中的现有工艺制造而无需任何附加的掩模和工艺步骤。

公开(公告)号：US08901644B2

公开(公告)日：2014-12-02

申请号：US13821944

申请日：2011-09-09

申请人： Ru Huang ,  Yujie Ai ,  Zhihua Hao ,  Shuangshuang Pu ,  Jiewen Fan ,  Shuai Sun ,  Runsheng Wang ,  Xiaoyan Xu

发明人： Ru Huang ,  Yujie Ai ,  Zhihua Hao ,  Shuangshuang Pu ,  Jiewen Fan ,  Shuai Sun ,  Runsheng Wang ,  Xiaoyan Xu

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/04 ,  H01L29/775 ,  H01L29/06 ,  H01L21/28 ,  H01L29/41 ,  H01L29/423

CPC分类号： H01L29/7827 ,  B82Y10/00 ,  H01L21/2815 ,  H01L29/04 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/0676 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/413 ,  H01L29/42376 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/775

摘要： Disclosed herein is a field effect transistor with a vertical channel and a fabrication method thereof. A channel region of the field effect transistor is a circular ring-shaped Si platform, which is formed over a substrate and perpendicular to the substrate; a source, which is made of polysilicon, is located at an upper end of the Si platform; a drain is disposed at an outside of a lower end of the circular ring-shaped Si platform; a gate is placed on an outer side surface of the circular ring-shaped Si platform; and an inside of the circular ring-shaped Si platform is filled with a dielectric material. In comparison with the conventional vertical structure MOSFET with a Si platform, the circular ring-shaped structure field effect transistor according to the invention can effectively suppress the short channel effect and improve the device performance.

摘要翻译： 本文公开了具有垂直沟道的场效应晶体管及其制造方法。 场效应晶体管的沟道区域是形成在衬底上并垂直于衬底的圆形环形Si平台; 由多晶硅制成的源头位于Si平台的上端; 在圆环状Si平台的下端的外侧配置有排水口， 在圆环状Si平台的外侧面上设置有闸门; 并且圆形环形Si平台的内部填充有电介质材料。 与传统的具有Si平台的垂直结构MOSFET相比，根据本发明的圆环形结构场效应晶体管可以有效地抑制短沟道效应并提高器件性能。

公开(公告)号：US08895980B2

公开(公告)日：2014-11-25

申请号：US13255087

申请日：2011-05-26

申请人： Ru Huang ,  Zhan Zhan ,  Qianqian Huang ,  Yangyuan Wang

发明人： Ru Huang ,  Zhan Zhan ,  Qianqian Huang ,  Yangyuan Wang

IPC分类号： H01L29/73 ,  H01L29/739 ,  H01L29/00

CPC分类号： H01L29/7391

摘要： The present invention discloses a tunneling current amplification transistor, which relates to an area of field effect transistor logic devices in CMOS ultra large scale semiconductor integrated circuits (ULSI). The tunneling current amplification transistor includes a semiconductor substrate, a gate dielectric layer, an emitter, a drain, a floating tunneling base and a control gate, wherein the drain, the floating tunneling base and the control gate forms a conventional TFET structure, and a doping type of the emitter is opposite to that of the floating tunneling base. A position of the emitter is at the other side of the floating tunneling base with respect to the drain. A type of the semiconductor between the emitter and the floating tunneling base is the same as that of the floating tunneling base. As compared with the conventional TFET, the tunneling current amplification transistor of the present invention can increase the on-current of the device effectively and increase the driving capability of the device.

摘要翻译： 本发明公开了一种隧道电流放大晶体管，其涉及CMOS超大规模半导体集成电路（ULSI）中的场效应晶体管逻辑器件的面积。 隧道电流放大晶体管包括半导体衬底，栅极电介质层，发射极，漏极，浮动隧道基极和控制栅极，其中漏极，浮动隧道基极和控制栅极形成传统的TFET结构，以及 发射极的掺杂类型与浮动隧道基体的掺杂类型相反。 发射极的位置相对于漏极在浮动基底的另一侧。 发射极和浮动隧道基底之间的半导体类型与浮动隧道基底的相同。 与常规TFET相比，本发明的隧道电流放大晶体管可以有效地增加器件的导通电流，并提高器件的驱动能力。

公开(公告)号：US08673722B2

公开(公告)日：2014-03-18

申请号：US13255443

申请日：2011-03-23

申请人： Ru Huang ,  Quanxin Yun ,  Xia An ,  Yujie Al ,  Xing Zhang

发明人： Ru Huang ,  Quanxin Yun ,  Xia An ,  Yujie Al ,  Xing Zhang

IPC分类号： H01L21/336

CPC分类号： H01L29/0653 ,  H01L29/1083 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7848 ,  H01L29/7849

摘要： The present invention discloses a strained channel field effect transistor and a method for fabricating the same. The field effect transistor comprises a substrate, a source/drain, a gate dielectric layer, and a gate, characterized in that, an “L” shaped composite isolation layer, which envelops a part of a side face of the source/drain adjacent to a channel and the bottom of the source/drain, is arranged between the source/drain and the substrate; the composite isolation layer is divided into two layers, that is, an “L” shaped insulation thin layer contacting directly with the substrate and an “L” shaped high stress layer contacting directly with the source and the drain. The field effect transistor of such a structure improves the mobility of charge carriers by introducing stress into the channel by means of the high stress layer, while fundamentally improving the device structure of the field effect transistor and improving the short channel effect suppressing ability of the device.

摘要翻译： 本发明公开了一种应变通道场效应晶体管及其制造方法。 场效应晶体管包括衬底，源极/漏极，栅极电介质层和栅极，其特征在于，“L”形复合隔离层，其包围与源极/漏极相邻的侧面的一部分 沟道和源极/漏极的底部布置在源极/漏极和衬底之间; 复合隔离层分为两层，即与基板直接接触的“L”形绝缘薄层和与源极和漏极直接接触的“L”形高应力层。 这种结构的场效应晶体管通过高应力层向沟道中引入应力而提高了载流子的迁移率，同时从根本上改善了场效应晶体管的器件结构，提高了器件的短沟道效应抑制能力 。

公开(公告)号：US08592276B2

公开(公告)日：2013-11-26

申请号：US13501711

申请日：2011-11-18

申请人： Ru Huang ,  Jiewen Fan ,  Yujie Ai ,  Shuai Sun ,  Runsheng Wang ,  Jibin Zou ,  Xin Huang

发明人： Ru Huang ,  Jiewen Fan ,  Yujie Ai ,  Shuai Sun ,  Runsheng Wang ,  Jibin Zou ,  Xin Huang

IPC分类号： H01L21/336

CPC分类号： H01L29/0676 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/66439 ,  H01L29/775

摘要： The present invention discloses a fabrication method of a vertical silicon nanowire field effect transistor having a low parasitic resistance, which relates to a field of an ultra-large-integrated-circuit fabrication technology. As compared with a conventional planar field effect transistor, on one hand the vertical silicon nanowire field effect transistor fabricated by the present invention can provide a good ability for suppressing a short channel effect due to the excellent gate control ability caused by the one-dimensional structure, and reduce a leakage current and a drain-induced barrier lowering (DIBL). On the other hand, an area of the transistor is further reduced and an integration degree of an IC system is increased.

摘要翻译： 本发明公开了一种具有低寄生电阻的垂直硅纳米线场效应晶体管的制造方法，其涉及超大集成电路制造技术的领域。 与传统的平面场效应晶体管相比，一方面，本发明制造的垂直硅纳米线场效应晶体管可以提供良好的抑制由于一维结构引起的栅极控制能力的短通道效应的能力 ，并减少泄漏电流和漏极引起的屏障降低（DIBL）。 另一方面，晶体管的面积进一步减小，并且IC系统的集成度增加。

公开(公告)号：US20130161757A1

公开(公告)日：2013-06-27

申请号：US13582034

申请日：2012-04-16

申请人： Ru Huang ,  Fei Tan ,  Xia An ,  Qianqian Huang ,  Dong Yang ,  Xing Zhang

发明人： Ru Huang ,  Fei Tan ,  Xia An ,  Qianqian Huang ,  Dong Yang ,  Xing Zhang

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/02203 ,  H01L21/02216 ,  H01L21/3063 ,  H01L21/823878 ,  H01L27/0921

摘要： The present invention discloses a CMOS device of reducing charge sharing effect and a fabrication method thereof. The present invention has an additional isolation for trapping carriers disposed right below an isolation region. the material of the additional isolation region is porous silicon. Since porous silicon is a functional material of spongy structure by electrochemistry anodic oxidizing monocrystalline silicon wafer, there are a large number of microvoids and dangling bonds on the surface layer of the porous silicon. These defects may form defect states in a center of forbidden band of the porous silicon, the defect states may trap carriers so as to cause an increased resistance. And with an increase of density of corrosion current, porosity increases, and defects in the porous silicon increase. The present invention can reduce the charge sharing effect due to heavy ions by using a feature that the defect states in the porous silicon trap carriers, the formation of a shallow trench isolation (STI) region and a isolation region underneath only needs one time photolithography, and the process is simple, so that radioresistance performance of an integrated circuit may be greatly increased.

摘要翻译： 本发明公开了一种降低电荷共享效应的CMOS器件及其制造方法。 本发明对于设置在隔离区域正下方的捕获载体具有额外的隔离。 附加隔离区的材料是多孔硅。 由于多孔硅是通过电化学阳极氧化单晶硅晶片的海绵结构的功能材料，因此在多孔硅的表面层上存在大量微孔和悬挂键。 这些缺陷可能在多孔硅的禁带的中心形成缺陷状态，缺陷状态可能会捕获载体以引起增加的电阻。 随着腐蚀电流密度的增加，孔隙率增加，多孔硅中的缺陷增加。 本发明可以通过使用多孔硅捕集载体中的缺陷状态，浅沟槽隔离（STI）区域的形成和下面的隔离区域仅需要一次光刻来降低由于重离子引起的电荷共享效应， 并且该工艺简单，从而可以大大提高集成电路的射电阻性能。

公开(公告)号：US20130119445A1

公开(公告)日：2013-05-16

申请号：US13509170

申请日：2011-11-30

申请人： Ru Huang ,  Fei Tan ,  Xia An ,  Qianqian Huang ,  Dong Yang ,  Xing Zhang

发明人： Ru Huang ,  Fei Tan ,  Xia An ,  Qianqian Huang ,  Dong Yang ,  Xing Zhang

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/6653 ,  H01L29/1083 ,  H01L29/6659 ,  H01L29/7833

摘要： A CMOS device for reducing a radiation-induced charge collection and a method for fabricating the same. In the CMOS device, a heavily doped charge collection-suppressed region is disposed directly under the source region and the drain region. The region has a doping type opposite that of the source region and the drain region, and has a doping concentration not less than that of the source region and the drain region. The charge collection-suppressed region has a lateral part slightly less than or equal to that of the source region and the drain region, and has a lateral range toward to the channel not exceed the edges of the source region and the drain region. The CMOS device may greatly reduce a range of the funnel that appears under the action of a single particle, so that charges collected instantaneously under a force of an electric field may be reduced.

摘要翻译： 用于减少辐射诱导的电荷收集的CMOS器件及其制造方法。 在CMOS器件中，重掺杂电荷收集抑制区域直接设置在源极区域和漏极区域的正下方。 该区域具有与源极区域和漏极区域相反的掺杂类型，并且具有不小于源极区域和漏极区域的掺杂浓度。 电荷收集抑制区域具有稍小于或等于源极区域和漏极区域的横向部分，并且具有朝向沟道的横向范围不超过源极区域和漏极区域的边缘。 CMOS器件可以大大减少在单个粒子的作用下出现的漏斗的范围，使得可以在电场的力作用下立即收集的电荷减少。

公开(公告)号：US20120181585A1

公开(公告)日：2012-07-19

申请号：US13318333

申请日：2011-04-01

申请人： Ru Huang ,  Qianqian Huang ,  Zhan Zhan ,  Yangyuan Wang

发明人： Ru Huang ,  Qianqian Huang ,  Zhan Zhan ,  Yangyuan Wang

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/4238 ,  H01L29/66643 ,  H01L29/7391 ,  H01L29/7839

摘要： The present invention discloses a combined-source MOS transistor with a Schottky Barrier and a comb-shaped gate structure, and a method for manufacturing the same. The combined-source MOS transistor includes: a control gate electrode layer, a gate dielectric layer, a semiconductor substrate, a highly-doped source region and a highly-doped drain region, wherein a Schottky source region is connected to a side of the highly-doped source region which is far from a channel, one end of the control gate extends to the highly-doped source region, the extended gate region is an extension gate in a form of a comb-shaped and the original control gate region is a main gate; an active region covered by the extension gate is also a channel region, and is a substrate material; the highly-doped source region which is formed by highly doping is located on both sides of each comb finger of the extension gate; and a Schottky junction is formed at a location where the Schottky source region and the channel under the extension gate are located. As compared with an existing MOSFET, in the invention, a higher turn-on current, a lower leakage current and a steeper subthreshold slope may be obtained under the same process condition and the same active region size.

摘要翻译： 本发明公开了一种具有肖特基势垒和梳状栅极结构的组合源MOS晶体管及其制造方法。 组合源MOS晶体管包括：控制栅极电极层，栅极电介质层，半导体衬底，高掺杂源极区域和高掺杂漏极区域，其中肖特基源极区域连接到高度 远离通道的掺杂源极区域，控制栅极的一端延伸到高掺杂源极区域，延伸栅极区域是梳状形式的延伸栅极，并且原始控制栅极区域是 大门; 由延伸栅极覆盖的有源区域也是沟道区域，并且是衬底材料; 通过高掺杂形成的高掺杂源区位于延伸门的每个梳齿的两侧; 并且在肖特基源区域和延伸门下方的沟道所在的位置处形成肖特基结。 与现有的MOSFET相比，在本发明中，可以在相同的工艺条件和相同的有源区域尺寸下获得较高的导通电流，较低的漏电流和更陡的亚阈值斜率。