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42 条记录 (耗时 0.098 秒)

    Semiconductor memory with automatic refresh means
    22.
    发明授权
    Semiconductor memory with automatic refresh means 失效
    具有自动刷新功能的半导体存储器

    公开(公告)号：US4747082A

    公开(公告)日：1988-05-24

    申请号：US76174

    申请日：1987-07-21

    申请人： Osamu Minato ,  Toshiaki Masuhara ,  Katsuhiro Shimohigashi ,  Shoji Hanamura ,  Shigeru Honjyo ,  Nobuyuki Moriwaki ,  Fumio Kojima

    发明人： Osamu Minato ,  Toshiaki Masuhara ,  Katsuhiro Shimohigashi ,  Shoji Hanamura ,  Shigeru Honjyo ,  Nobuyuki Moriwaki ,  Fumio Kojima

    IPC分类号： G11C11/406 ,  G11C8/00

    CPC分类号： G11C11/406

    摘要： A semiconductor memory is provided with automatic refresh means including a timer, a refresh counter and a refresh buffer each formed on a semiconductor chip mounted with an asynchronous memory, for automatically performing a periodic refresh operation on the basis of a basic clock signal which is generated in response to the detection of a logical change in the output of the refresh counter. The automatic refresh counter includes means for performing one of a read operation and a write operation which are based upon a regular address signal asynchronous with the periodic refresh operation, in preference to the periodic refresh operation.

    摘要翻译： 半导体存储器设置有自动刷新装置，包括定时器，刷新计数器和刷新缓冲器，每个形成在安装有异步存储器的半导体芯片上，用于基于生成的基本时钟信号自动执行周期性刷新操作 响应于对刷新计数器的输出的逻辑改变的检测。 自动刷新计数器包括优先于周期性刷新操作执行基于与周期性刷新操作异步的常规地址信号的读操作和写操作之一的装置。

    Semiconductor memory device and sense amplifier
    24.
    发明授权
    Semiconductor memory device and sense amplifier 失效
    半导体存储器件和读出放大器

    公开(公告)号：US4841486A

    公开(公告)日：1989-06-20

    申请号：US946776

    申请日：1986-12-29

    申请人： Osamu Minato ,  Toshiaki Masuhara ,  Koichiro Ishibashi ,  Shoji Hanamura ,  Shigeru Honjyo ,  Nobuyuki Moriwaki

    发明人： Osamu Minato ,  Toshiaki Masuhara ,  Koichiro Ishibashi ,  Shoji Hanamura ,  Shigeru Honjyo ,  Nobuyuki Moriwaki

    IPC分类号： H01L27/11 ,  G11C7/06 ,  G11C11/416 ,  G11C11/419 ,  H01L21/8244 ,  H01L27/10

    CPC分类号： G11C11/419 ,  G11C7/062

    摘要： A semiconductor memory device having a memory plane defined by a plurality of memory cells, a decoder line for accessing the memory cells, a common data line on which a signal output from an accessed memory cell is collected, and a sense amplifier for amplifying the signal collected on the common data line. The sense amplifier has an amplifying circuit portion which is composed of a pair of common-collector type bipolar transistors supplied with the signal collected on the common data line as a differential input, and a plurality of MOS transistors for converting a change in current into a change in voltage. Each of the MOS transistors has a lightly-doped drain structure.

    摘要翻译： 一种具有由多个存储单元限定的存储器平面的半导体存储器件，用于访问存储器单元的解码器线，从所访问的存储单元输出的信号被收集的公共数据线，以及用于放大该信号的读出放大器 在公共数据线上收集。 读出放大器具有放大电路部分，该放大电路部分由一对公共集电极型双极晶体管构成，该一对公共集电极型双极晶体管被提供有作为差分输入的公共数据线上收集的信号，以及多个MOS晶体管，用于将电流变化转换为 电压变化。 每个MOS晶体管具有轻掺杂漏极结构。

    MIS-FETs isolated on common substrate
    25.
    发明授权
    MIS-FETs isolated on common substrate 失效
    在公共基板上隔离的MIS-FET

    公开(公告)号：US4015281A

    公开(公告)日：1977-03-29

    申请号：US121375

    申请日：1971-03-05

    申请人： Minoru Nagata ,  Toshiaki Masuhara ,  Masaharu Kubo ,  Norikazu Hashimoto

    发明人： Minoru Nagata ,  Toshiaki Masuhara ,  Masaharu Kubo ,  Norikazu Hashimoto

    IPC分类号： H01L21/765 ,  H01L27/088 ,  H01L29/51 ,  H01L27/02

    CPC分类号： H01L29/511 ,  H01L21/765 ,  H01L27/0883

    摘要： An enhancement-type and a depletion-type metal-insulator-semiconductor field effect transistor are formed on a common substrate of silicon and are electrically isolated from each other by a plurality of layers including, for example, a first layer of SiO.sub.2, a second layer of Al.sub.2 O.sub.3 capable of inducing holes in the surface portion of the substrate, and a third layer of SiO.sub.2, and the relation between the thicknesses of these layers is suitably selected for attaining the satisfactory isolation between these transistors.

    摘要翻译： 增强型和耗尽型金属 - 绝缘体 - 半导体场效应晶体管形成在公共的硅衬底上，并且通过多个层彼此电隔离，所述多个层包括例如第一SiO 2层，第二层 能够在衬底的表面部分中引入空穴的Al 2 O 3层和SiO 3层，并且适当地选择这些层的厚度之间的关系以获得这些晶体管之间的令人满意的隔离。

    Interconnection structure for semiconductor integrated circuits
    27.
    发明授权
    Interconnection structure for semiconductor integrated circuits 失效
    半导体集成电路的互连结构

    公开(公告)号：US4199778A

    公开(公告)日：1980-04-22

    申请号：US843366

    申请日：1977-10-19

    申请人： Toshiaki Masuhara ,  Tokumasa Yasui ,  Yoshio Sakai ,  Joh Nakajima ,  Yasunobu Kosa ,  Satoshi Meguro ,  Masaharu Kubo

    发明人： Toshiaki Masuhara ,  Tokumasa Yasui ,  Yoshio Sakai ,  Joh Nakajima ,  Yasunobu Kosa ,  Satoshi Meguro ,  Masaharu Kubo

    IPC分类号： H01L21/763 ,  H01L21/31 ,  H01L21/3205 ,  H01L21/3215 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532 ,  H01L29/04 ,  H01L23/48 ,  H01L29/44

    CPC分类号： H01L21/32155 ,  H01L21/76889 ,  H01L23/53271 ,  H01L2924/0002

    摘要： In a semiconductor integrated circuit having polycrystalline silicon interconnections and metal interconnections, a low resistance layer, containing impurities to a high concentration for the polycrystalline silicon interconnections, is formed in predetermined parts of an undoped polycrystalline silicon layer which is deposited on a first insulator film on a semiconductor substrate, a second insulator film is deposited on the polycrystalline silicon layer under the state under which the undoped parts are left at least around through-holes to be formed, and the metal interconnections at least parts of which run in a direction intersecting the polycrystalline silicon interconnections are provided on the second insulator film, the necessary contacts between the metal interconnections and the polycrystalline silicon interconnections being made through the through-holes provided in the second insulator film in correspondence with the intersecting parts of both the interconnections.

    摘要翻译： 在具有多晶硅互连和金属互连的半导体集成电路中，在未掺杂的多晶硅层的预定部分中形成在多晶硅互连中含有高浓度的杂质的低电阻层，其沉积在第一绝缘膜上 半导体衬底，第二绝缘膜沉积在多晶硅层上，在未被掺杂的部分至少留在待形成的通孔周围的状态下，并且其至少部分的金属互连在与 多晶硅互连设置在第二绝缘膜上，金属互连和多晶硅互连之间的必要接触通过设置在第二绝缘膜中的通孔形成，与两个互连的相交部分相对应。

    Semiconductor memory device
    29.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US4942556A

    公开(公告)日：1990-07-17

    申请号：US377181

    申请日：1989-07-10

    申请人： Toshio Sasaki ,  Masakazu Aoki ,  Masashi Horiguchi ,  Yoshinobu Nakagome ,  Shinichi Ikenaga ,  Toshiaki Masuhara

    发明人： Toshio Sasaki ,  Masakazu Aoki ,  Masashi Horiguchi ,  Yoshinobu Nakagome ,  Shinichi Ikenaga ,  Toshiaki Masuhara

    IPC分类号： G11C15/04 ,  G11C29/00 ,  G11C29/44

    CPC分类号： G11C29/76 ,  G11C15/04 ,  G11C15/046 ,  G11C29/44

    摘要： In a defect relieving technology which replaces defective memory cells of a semiconductor memory device by spare memory cells, use is made of an associative memory. Address information of a defective memory cell is stored as a reference data of the associative memory, and new address information of a spare memory cell is written down as output data of the associative memory. A variety of improvements are made to the associative memory. For instance, a plurality of coincidence detection signal lines of the associative memory are divided into at least two groups, and one group among them is selected by switching means. Reference data of the associative memory comprises three values consisting of binary information of "0" and "1", and don't care value "X". The associative memory further includes a plurality of electrically programable non-volatile semiconductor memory elements.

    摘要翻译： 在通过备用存储器单元代替半导体存储器件的缺陷存储单元的缺陷解除技术中，使用关联存储器。 存储有缺陷的存储单元的地址信息被存储为关联存储器的参考数据，并且备用存储单元的新地址信息被写入作为关联存储器的输出数据。 对联想记忆进行了各种改进。 例如，关联存储器的多个符合检测信号线被划分为至少两组，其中一组由切换装置选择。 关联存储器的参考数据包括由“0”和“1”的二进制信息组成的三个值，并且不关心值“X”。 关联存储器还包括多个可电可编程的非易失性半导体存储器元件。