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公开(公告)号：US08203215B2
公开(公告)日：2012-06-19
申请号：US12835291
申请日：2010-07-13
IPC分类号： H01L23/48
CPC分类号： H01L23/522 , H01L21/563 , H01L21/6835 , H01L23/544 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/24 , H01L24/25 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/81 , H01L24/82 , H01L24/83 , H01L24/92 , H01L24/94 , H01L24/95 , H01L24/96 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L25/16 , H01L25/50 , H01L2221/68327 , H01L2223/54406 , H01L2223/54433 , H01L2223/54453 , H01L2224/0231 , H01L2224/02311 , H01L2224/02313 , H01L2224/02321 , H01L2224/02371 , H01L2224/02375 , H01L2224/02379 , H01L2224/02381 , H01L2224/0239 , H01L2224/0345 , H01L2224/0346 , H01L2224/0401 , H01L2224/04026 , H01L2224/05008 , H01L2224/05644 , H01L2224/05647 , H01L2224/1146 , H01L2224/13144 , H01L2224/16148 , H01L2224/24011 , H01L2224/24146 , H01L2224/245 , H01L2224/2746 , H01L2224/29111 , H01L2224/29144 , H01L2224/2919 , H01L2224/32148 , H01L2224/81121 , H01L2224/8113 , H01L2224/81191 , H01L2224/81193 , H01L2224/81203 , H01L2224/81815 , H01L2224/82005 , H01L2224/821 , H01L2224/82101 , H01L2224/82106 , H01L2224/83005 , H01L2224/8313 , H01L2224/83191 , H01L2224/83193 , H01L2224/83203 , H01L2224/83815 , H01L2224/8385 , H01L2224/9202 , H01L2224/92244 , H01L2224/94 , H01L2224/95001 , H01L2224/96 , H01L2224/97 , H01L2225/06551 , H01L2225/06565 , H01L2225/1058 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01037 , H01L2924/0105 , H01L2924/01058 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2224/81 , H01L2224/83 , H01L2224/82 , H01L2924/00 , H01L2221/68304
摘要： A layered chip package includes a main body and wiring, the wiring including a plurality of wires disposed on a side surface of the main body. The main body includes a main part and a plurality of terminals. The main part includes a plurality of layer portions stacked. The terminals are disposed on at least either one of the top and bottom surfaces of the main part and electrically connected to the wires. Each of the layer portions includes a semiconductor chip, and a plurality of electrodes that are electrically connected to the wires. The electrodes include a plurality of first electrodes that are intended to establish electrical connection to the semiconductor chip, and a plurality of second electrodes that are not in contact with the semiconductor chip. In at least one of the layer portions, the first electrodes are in contact with and electrically connected to the semiconductor chip.
摘要翻译： 分层芯片封装包括主体和布线，所述布线包括设置在主体的侧表面上的多根布线。 主体包括主要部分和多个端子。 主要部分包括堆叠的多个层部分。 端子设置在主要部件的顶表面和底表面中的至少一个中并电连接到电线。 每个层部分包括半导体芯片和电连接到导线的多个电极。 电极包括旨在建立与半导体芯片的电连接的多个第一电极和不与半导体芯片接触的多个第二电极。 在至少一个层部分中，第一电极与半导体芯片接触并电连接。
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公开(公告)号：US08171607B2
公开(公告)日：2012-05-08
申请号：US12363140
申请日：2009-01-30
CPC分类号： H01G4/30 , H01G4/012 , H01G4/232 , Y10T29/43 , Y10T29/435
摘要： In a method of manufacturing ceramic capacitor according to the present invention, a pair of interdigitated internal electrodes are arranged perpendicularly to the surface of the substrate, subsequent to which the respective end faces of this pair of internal electrodes are exposed, and a pair of external electrodes are formed at these exposed end faces. In this method of manufacturing ceramic capacitor, formation of the external electrodes on the end faces of the respective internal electrodes, with these internal electrodes being interdigitately integrally-formed and the end faces thereof being exposed, it possible to reliably and easily form the external electrodes.
摘要翻译： 在根据本发明的陶瓷电容器的制造方法中，一对叉指的内部电极垂直于衬底的表面布置，随后暴露出这对内部电极的各个端面，并且一对外部 在这些暴露的端面处形成电极。 在这种制造陶瓷电容器的方法中，在各个内部电极的端面上形成外部电极，这些内部电极被互相整体形成并且其端面被暴露，可以可靠且容易地形成外部电极 。
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公开(公告)号：US20120032318A1
公开(公告)日：2012-02-09
申请号：US12852767
申请日：2010-08-09
CPC分类号： H01L25/50 , H01L23/5382 , H01L24/01 , H01L25/0657 , H01L2225/06527 , H01L2225/06551 , H01L2924/07802 , H01L2924/00
摘要： A layered chip package includes a main body, and wiring that includes a plurality of wires disposed on a side surface of the main body. The main body includes: a main part including a plurality of layer portions; a plurality of first terminals disposed on the top surface of the main part and connected to the wiring; and a plurality of second terminals disposed on the bottom surface of the main part and connected to the wiring. Each layer portion includes a semiconductor chip. The plurality of second terminals are positioned to overlap the plurality of first terminals as viewed in a direction perpendicular to the top surface of the main body. A plurality of pairs of first and second terminals that are electrically connected via the wires include a plurality of pairs of a first terminal and a second terminal that are positioned not to overlap each other.
摘要翻译： 分层芯片封装包括主体和布线，其包括布置在主体的侧表面上的多根导线。 主体包括：主要部分，包括多个层部分; 多个第一端子，其设置在所述主体部的上表面并与所述布线连接; 以及多个第二端子，其设置在所述主体部的底面并与所述布线连接。 每个层部分包括半导体芯片。 多个第二端子被定位成在垂直于主体顶表面的方向上与多个第一端子重叠。 经由导线电连接的多对第一和第二端子包括定位为不彼此重叠的多对第一端子和第二端子。
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公开(公告)号：US20110068456A1
公开(公告)日：2011-03-24
申请号：US12585778
申请日：2009-09-24
IPC分类号： H01L25/065 , H01L21/50 , H01L21/66
CPC分类号： H01L24/94 , H01L23/481 , H01L24/11 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/05554 , H01L2224/0557 , H01L2224/1147 , H01L2224/13099 , H01L2225/06513 , H01L2225/06541 , H01L2225/06596 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/3025 , H01L2224/05552
摘要： A layered chip package includes a plurality of layer portions that are stacked, each of the layer portions including a semiconductor chip. The plurality of layer portions include at least one first-type layer portion and at least one second-type layer portion. The semiconductor chip has a circuit, a plurality of electrode pads electrically connected to the circuit, and a plurality of through electrodes. In every vertically adjacent two of the layer portions, the plurality of through electrodes of the semiconductor chip of one of the two layer portions are electrically connected to the respective corresponding through electrodes of the semiconductor chip of the other of the two layer portions. The first-type layer portion includes a plurality of wires for electrically connecting the plurality of through electrodes to the respective corresponding electrode pads, whereas the second-type layer portion does not include the wires.
摘要翻译： 分层芯片封装包括堆叠的多个层部分，每个层部分包括半导体芯片。 多个层部分包括至少一个第一类型层部分和至少一个第二类型的部分。 半导体芯片具有电路，电连接到电路的多个电极焊盘以及多个贯通电极。 在每个垂直相邻的两个层部分中，两个层部分中的一个的半导体芯片的多个通孔电连接到两个层部分中另一个的半导体芯片的相应的贯通电极。 第一型层部分包括用于将多个贯通电极电连接到各个对应的电极焊盘的多条导线，而第二型层部分不包括导线。
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公开(公告)号：US07902677B1
公开(公告)日：2011-03-08
申请号：US12588808
申请日：2009-10-28
CPC分类号： H01L24/96 , H01L21/6835 , H01L23/3171 , H01L24/06 , H01L24/16 , H01L24/25 , H01L24/29 , H01L24/73 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2221/68359 , H01L2224/0401 , H01L2224/04105 , H01L2224/05553 , H01L2224/05647 , H01L2224/12105 , H01L2224/13099 , H01L2224/32145 , H01L2224/73267 , H01L2224/82 , H01L2224/92244 , H01L2225/06513 , H01L2225/06551 , H01L2225/1035 , H01L2225/1064 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/078 , H01L2924/07802 , H01L2924/14 , H01L2924/18162 , H01L2924/30105 , H01L2924/3025 , H01L2924/00014 , H01L2924/00
摘要： A composite layered chip package includes a plurality of subpackages stacked. Each subpackage includes a main body, and wiring disposed on a side surface of the main body. The main body has a main part that includes at least one first-type layer portion. For any two vertically adjacent subpackages, the main body of the lower subpackage has a plurality of first terminals that are arranged on the top surface of the main part, while the main body of the upper subpackage has a plurality of second terminals that are arranged on the bottom surface of the main part. The main part of the main body of at least one of the plurality of subpackages includes at least one second-type layer portion. The first-type layer portion includes a conforming semiconductor chip, while the second-type layer portion includes a defective semiconductor chip.
摘要翻译： 复合分层芯片封装包括堆叠的多个子封装。 每个子包包括主体和布置在主体的侧表面上的布线。 主体具有包括至少一个第一类型层部分的主要部分。 对于任何两个垂直相邻的子包装，下部子包装的主体具有布置在主要部件的顶表面上的多个第一端子，而上部子包装的主体具有多个第二端子，第二端子布置在 主要部分的底面。 多个子包中的至少一个子包的主体的主要部分包括至少一个第二类型层部分。 第一型层部分包括一致的半导体芯片，而第二型层部分包括有缺陷的半导体芯片。
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公开(公告)号：US20100195264A1
公开(公告)日：2010-08-05
申请号：US12363188
申请日：2009-01-30
IPC分类号： H01G4/12
摘要： In a ceramic capacitor according to the present invention, an interdiginated pair of internal electrodes are arranged, on a substrate, perpendicular to a surface of the substrate, and a ceramic dielectric member is filled into a gap between this pair of internal electrodes. For this reason, the dimensions of the internal electrodes do not substantially change before and/or after the formation of the ceramic dielectric member, whereby the dimensions formed at the time of internal electrode can be maintained. According to this ceramic capacitor, since the internal electrode dimensions can be easily controlled like this, dimensional control of internal electrode spacing can also be easily carried out.
摘要翻译： 在根据本发明的陶瓷电容器中，在基板上垂直于基板的表面布置有叉指对的内部电极，并且将陶瓷电介质部件填充到该一对内部电极之间的间隙中。 因此，在形成陶瓷电介质部件之前和/或之后，内部电极的尺寸基本上不会发生变化，从而可以保持在内部电极时形成的尺寸。 根据该陶瓷电容器，由于可以容易地控制内部电极尺寸，因此也可以容易地进行内部电极间隔的尺寸控制。
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公开(公告)号：US08513034B2
公开(公告)日：2013-08-20
申请号：US13064880
申请日：2011-04-22
申请人： Yoshitaka Sasaki , Hiroyuki Ito , Tatsuya Harada , Nobuyuki Okuzawa , Satoru Sueki , Hiroshi Ikejima
发明人： Yoshitaka Sasaki , Hiroyuki Ito , Tatsuya Harada , Nobuyuki Okuzawa , Satoru Sueki , Hiroshi Ikejima
IPC分类号： H01L21/66
CPC分类号： H01L25/0657 , G11C16/102 , H01L24/01 , H01L25/50 , H01L2224/48091 , H01L2225/06527 , H01L2225/06551 , H01L2225/06596 , H01L2924/07802 , H01L2924/181 , H01L2924/30107 , H01L2924/00014 , H01L2924/00
摘要： A method of manufacturing a layered chip package that includes a main body, and wiring disposed on a side surface of the main body. The main body includes a plurality of layer portions. The method includes fabricating a plurality of substructures, and completing the layered chip package by fabricating the main body using the plurality of substructures and by forming the wiring on the main body. Each substructure is fabricated through the steps of: fabricating a pre-substructure wafer including a plurality of pre-semiconductor-chip portions aligned; distinguishing between a normally functioning pre-semiconductor-chip portion and a malfunctioning pre-semiconductor-chip portion among the plurality of pre-semiconductor-chip portions included in the pre-substructure wafer; and forming electrodes connected to the normally functioning pre-semiconductor-chip portion and having respective end faces located in the side surface of the main body on which the wiring is disposed, without forming any electrode connected to the malfunctioning pre-semiconductor-chip portion.
摘要翻译： 一种制造包括主体和布置在主体的侧表面上的布线的分层芯片封装的方法。 主体包括多个层部分。 该方法包括制造多个子结构，并且通过使用多个子结构制造主体并且通过在主体上形成布线来完成分层芯片封装。 每个子结构通过以下步骤制造：制造包括对准的多个预半导体芯片部分的预底晶片; 区分预结晶晶片中包含的多个预半导体芯片部分中的正常工作的预半导体芯片部分和故障的预半导体芯片部分; 以及形成连接到正常工作的预半导体芯片部分并且具有位于布置有布线的主体的侧表面中的各个端面的电极，而不形成连接到故障的预半导体芯片部分的任何电极。
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公开(公告)号：US07964976B2
公开(公告)日：2011-06-21
申请号：US12222955
申请日：2008-08-20
申请人： Yoshitaka Sasaki , Hiroyuki Ito , Tatsuya Harada , Nobuyuki Okuzawa , Satoru Sueki , Hiroshi Ikejima
发明人： Yoshitaka Sasaki , Hiroyuki Ito , Tatsuya Harada , Nobuyuki Okuzawa , Satoru Sueki , Hiroshi Ikejima
IPC分类号： H01L29/40
CPC分类号： H01L25/0657 , G11C16/102 , H01L24/01 , H01L25/50 , H01L2224/48091 , H01L2225/06527 , H01L2225/06551 , H01L2225/06596 , H01L2924/07802 , H01L2924/181 , H01L2924/30107 , H01L2924/00014 , H01L2924/00
摘要： A layered chip package includes a main body including a plurality of layer portions, and wiring disposed on a side surface of the main body. The plurality of layer portions include at least one layer portion of a first type and at least one layer portion of a second type. The layer portions of the first and second types each include a semiconductor chip. The layer portion of the first type further includes a plurality of electrodes each connected to the semiconductor chip and each having an end face located at the side surface of the main body on which the wiring is disposed, whereas the layer portion of the second type does not include any electrode connected to the semiconductor chip and having an end face located at the side surface of the main body on which the wiring is disposed. The wiring is connected to the end face of each of the plurality of electrodes.
摘要翻译： 层状芯片封装包括具有多个层部分的主体和布置在主体的侧表面上的布线。 多个层部分包括第一类型的至少一个层部分和第二类型的至少一个层部分。 第一和第二类型的层部分都包括半导体芯片。 第一类型的层部分还包括多个电极，每个电极连接到半导体芯片，并且每个电极具有位于布置有布线的主体的侧表面的端面，而第二类型的层部分 不包括连接到半导体芯片并且具有位于布置有布线的主体的侧表面的端面的任何电极。 布线连接到多个电极中的每一个的端面。
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公开(公告)号：US08154116B2
公开(公告)日：2012-04-10
申请号：US12289745
申请日：2008-11-03
申请人： Yoshitaka Sasaki , Hiroyuki Ito , Tatsuya Harada , Nobuyuki Okuzawa , Satoru Sueki , Hiroshi Ikejima
发明人： Yoshitaka Sasaki , Hiroyuki Ito , Tatsuya Harada , Nobuyuki Okuzawa , Satoru Sueki , Hiroshi Ikejima
CPC分类号： H01L25/0657 , H01L23/367 , H01L23/427 , H01L25/50 , H01L2224/24145 , H01L2225/0651 , H01L2225/06551 , H01L2225/06589
摘要： A layered chip package includes: a plurality of layer portions stacked, each of the layer portions including a semiconductor chip; and a heat sink. Each of the plurality of layer portions has a top surface, a bottom surface, and four side surfaces. The heat sink has at least one first portion, and a second portion coupled to the at least one first portion. The at least one first portion is adjacent to the top surface or the bottom surface of at least one of the layer portions. The second portion is adjacent to one of the side surfaces of each of at least two of the plurality of layer portions.
摘要翻译： 层叠芯片封装包括：层叠多个层部，每个层部分包括半导体芯片; 和散热器。 多个层部分中的每一个具有顶表面，底表面和四个侧表面。 散热器具有至少一个第一部分，以及耦合到该至少一个第一部分的第二部分。 所述至少一个第一部分邻近所述层部分中的至少一个的顶表面或底表面。 第二部分与多个层部分中的至少两个层部分中的每一个的一个侧表面相邻。
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公开(公告)号：US20110201137A1
公开(公告)日：2011-08-18
申请号：US13064880
申请日：2011-04-22
申请人： Yoshitaka Sasaki , Hiroyuki Ito , Tatsuya Harada , Nobuyuki Okuzawa , Satoru Sueki , Hiroshi Ikejima
发明人： Yoshitaka Sasaki , Hiroyuki Ito , Tatsuya Harada , Nobuyuki Okuzawa , Satoru Sueki , Hiroshi Ikejima
IPC分类号： H01L21/66
CPC分类号： H01L25/0657 , G11C16/102 , H01L24/01 , H01L25/50 , H01L2224/48091 , H01L2225/06527 , H01L2225/06551 , H01L2225/06596 , H01L2924/07802 , H01L2924/181 , H01L2924/30107 , H01L2924/00014 , H01L2924/00
摘要： A method of manufacturing a layered chip package that includes a main body, and wiring disposed on a side surface of the main body. The main body includes a plurality of layer portions. The method includes fabricating a plurality of substructures, and completing the layered chip package by fabricating the main body using the plurality of substructures and by forming the wiring on the main body. Each substructure is fabricated through the steps of: fabricating a pre-substructure wafer including a plurality of pre-semiconductor-chip portions aligned; distinguishing between a normally functioning pre-semiconductor-chip portion and a malfunctioning pre-semiconductor-chip portion among the plurality of pre-semiconductor-chip portions included in the pre-substructure wafer; and forming electrodes connected to the normally functioning pre-semiconductor-chip portion and having respective end faces located in the side surface of the main body on which the wiring is disposed, without forming any electrode connected to the malfunctioning pre-semiconductor-chip portion.
摘要翻译： 一种制造包括主体和布置在主体的侧表面上的布线的分层芯片封装的方法。 主体包括多个层部分。 该方法包括制造多个子结构，并且通过使用多个子结构制造主体并且通过在主体上形成布线来完成分层芯片封装。 每个子结构通过以下步骤制造：制造包括对准的多个预半导体芯片部分的预底晶片; 区分预结晶晶片中包含的多个预半导体芯片部分中的正常工作的预半导体芯片部分和故障的预半导体芯片部分; 以及形成连接到正常工作的预半导体芯片部分并且具有位于布置有布线的主体的侧表面中的各个端面的电极，而不形成连接到故障的预半导体芯片部分的任何电极。
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