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110 条记录 (耗时 0.035 秒)

    Semiconductor integrated circuit device and process for manufacturing the same
    23.
    发明授权
    Semiconductor integrated circuit device and process for manufacturing the same 有权
    半导体集成电路器件及其制造方法

    公开(公告)号：US06770535B2

    公开(公告)日：2004-08-03

    申请号：US09767830

    申请日：2001-01-24

    申请人： Satoru Yamada ,  Kiyonori Oyu ,  Shinichiro Kimura

    发明人： Satoru Yamada ,  Kiyonori Oyu ,  Shinichiro Kimura

    IPC分类号： H01L21336

    CPC分类号： H01L27/10876 ,  H01L21/763 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10888 ,  H01L27/10894

    摘要： A reduction of the junction electric field intensity is accomplished in the semiconductor regions for the sources and drains of field effects transistors. For this purpose, a structure is provided where the gate electrodes 9 of the MIS.FETQs for memory cell selection of a DRAM are buried within the trenches 7a and 7b created in the semiconductor substrate 1. The bottom corners within the trench 7b are rounded so as to have a radius of curvature in accordance with the sub-threshold coefficient of the MIS.FETQs for memory cell selection. In addition, the gate insulating film 8 within the trench 7b is made to have a laminated structure of a thermal oxide film and a CVD film.

    摘要翻译： 在场效应晶体管的源极和漏极的半导体区域中实现结电场强度的降低。 为此，提供了一种结构，其中用于DRAM的存储单元选择的MIS.FETQ的栅电极9被埋在在半导体衬底1中形成的沟槽7a和7b内。沟槽7b内的底角被倒圆 具有根据用于存储器单元选择的MIS.FETQ的子阈值系数的曲率半径。 此外，使沟槽7b内的栅极绝缘膜8具有热氧化膜和CVD膜的层叠结构。

    Semiconductor memory device
    26.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5591998A

    公开(公告)日：1997-01-07

    申请号：US443106

    申请日：1995-05-17

    申请人： Shinichiro Kimura ,  Naotaka Hashimoto ,  Yoshio Sakai ,  Tokuo Kure ,  Yoshifumi Kawamoto ,  Toru Kaga ,  Eiji Takeda

    发明人： Shinichiro Kimura ,  Naotaka Hashimoto ,  Yoshio Sakai ,  Tokuo Kure ,  Yoshifumi Kawamoto ,  Toru Kaga ,  Eiji Takeda

    IPC分类号： H01L27/108 ,  H01L29/417 ,  H01L29/45

    CPC分类号： H01L27/10808 ,  H01L27/10817 ,  H01L29/41775 ,  H01L29/456

    摘要： A semiconductor memory device having STC cells wherein the major portions of active regions consisting of channel-forming portions are inclined at an angle of 45 degrees with respect to word lines and bit lines that meet at right angles with each other, thereby enabling the storage capacity portions to be arranged very densely and a sufficiently large capacity to be maintained with very small cell areas. Since the storage capacity portions are formed even on the bit lines, the bit lines are shielded, so that the capacity decreases between the bit lines and, hence, the memory array noise decreases. It is also possible to design the charge storage capacity portion so that a part of thereof has a form of a wall substantially vertical to the substrate in order to increase the capacity.

    摘要翻译： 具有STC单元的半导体存储器件，其中由沟道形成部分组成的有源区的主要部分相对于彼此成直角相交的字线和位线以45度的角度倾斜，从而使得存储容量 部分布置非常密集，并且具有足够大的容量以保持非常小的单元格区域。 由于存储容量部分甚至在位线上形成，所以位线被屏蔽，使得位线之间的容量减小，因此存储器阵列噪声减小。 也可以设计电荷存储容量部分，使得其一部分具有基本上垂直于衬底的壁的形式，以增加容量。

    Semiconductor memory device having stacked capacitors
    27.
    发明授权
    Semiconductor memory device having stacked capacitors 失效
    具有层叠电容器的半导体存储器件

    公开(公告)号：US5583358A

    公开(公告)日：1996-12-10

    申请号：US324352

    申请日：1994-10-17

    申请人： Shinichiro Kimura ,  Naotaka Hashimoto ,  Yoshio Sakai ,  Tokuo Kure ,  Yoshifumi Kawamoto ,  Toru Kaga ,  Eiji Takeda

    发明人： Shinichiro Kimura ,  Naotaka Hashimoto ,  Yoshio Sakai ,  Tokuo Kure ,  Yoshifumi Kawamoto ,  Toru Kaga ,  Eiji Takeda

    IPC分类号： H01L27/108 ,  H01L29/417 ,  H01L29/45

    CPC分类号： H01L27/10808 ,  H01L27/10817 ,  H01L29/41775 ,  H01L29/456

    摘要： A semiconductor memory device having STC cells wherein the major portions of active regions consisting of channel-forming portions are inclined at an angle of 45 degrees with respect to word lines and bit lines that meet at right angles with each other, thereby enabling the storage capacity portions to be arranged very densely and a sufficiently large capacity to be maintained with very small cell areas. Since the storage capacity portions are formed even on the bit lines, the bit lines are shielded, so that the capacity decreases between the bit lines and, hence, the memory array noise decreases. It is also possible to design the charge storage capacity portion so that a part of thereof has a form of a wall substantially vertical to the substrate in order to increase the capacity.

    摘要翻译： 具有STC单元的半导体存储器件，其中由沟道形成部分组成的有源区的主要部分相对于彼此成直角相交的字线和位线以45度的角度倾斜，从而使得存储容量 部分布置非常密集，并且具有足够大的容量以保持非常小的单元格区域。 由于存储容量部分甚至在位线上形成，所以位线被屏蔽，使得位线之间的容量减小，因此存储器阵列噪声减小。 也可以设计电荷存储容量部分，使得其一部分具有基本上垂直于衬底的壁的形式，以增加容量。

    Semiconductor memory device having stacked capacitor cells
    29.
    发明授权
    Semiconductor memory device having stacked capacitor cells 失效
    具有层叠电容器单元的半导体存储器件

    公开(公告)号：US5140389A

    公开(公告)日：1992-08-18

    申请号：US475148

    申请日：1990-02-05

    申请人： Shinichiro Kimura ,  Naotaka Hashimoto ,  Yoshio Sakai ,  Tokuo Kure ,  Yoshifumi Kawamoto ,  Toru Kaga ,  Eiji Takeda

    发明人： Shinichiro Kimura ,  Naotaka Hashimoto ,  Yoshio Sakai ,  Tokuo Kure ,  Yoshifumi Kawamoto ,  Toru Kaga ,  Eiji Takeda

    IPC分类号： H01L27/108

    CPC分类号： H01L27/10817

    摘要： A semiconductor memory device having STC cells wherein the major portions of active regions consisting of channel-forming portions are inclined at an angle of 45 degrees with respect to word lines and bit lines that meet at right angles with each other, thereby enabling the storage capacitor portions to be arranged very densely and a sufficiently large capacitance to be maintained with very small cell areas. Since the storage capacitor portions are formed even on the bit lines, the bit lines are shielded, so that the capacitance decreases between the bit lines and, hence, the memory array noise decreases. It is also possible to design the charge storage capacitor portion so that a part thereof is in the form of a wall substantially vertical to the substrate in order to increase the capacitance.

    摘要翻译： 具有STC单元的半导体存储器件，其中由沟道形成部分组成的有源区的主要部分相对于彼此成直角相交的字线和位线以45度的角度倾斜，从而使得存储电容器 要非常密集地布置的部分和足够大的电容以保持非常小的电池区域。 由于存储电容器部分甚至在位线上形成，所以位线被屏蔽，使得位线之间的电容减小，因此存储器阵列噪声减小。 也可以设计电荷存储电容器部分，使得其一部分呈基本上垂直于衬底的壁的形式，以增加电容。

    Semiconductor memory having stacked capacitor
    30.
    发明授权
    Semiconductor memory having stacked capacitor 失效
    半导体存储器具有层叠电容

    公开(公告)号：US5012310A

    公开(公告)日：1991-04-30

    申请号：US566315

    申请日：1990-08-13

    申请人： Shinichiro Kimura ,  Yoshifumi Kawamoto ,  Toru Kaga ,  Hideo Sunami

    发明人： Shinichiro Kimura ,  Yoshifumi Kawamoto ,  Toru Kaga ,  Hideo Sunami

    IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/10808

    摘要： A megabit dynamic random access memory realizing high integration and high reliability is disclosed. The need for an allowance for photomask alignment which is carried out to produce a stacked capacitor memory cell is eliminated. The plate electrode of each memory cell is isolated from the corresponding data line in a memory array by means of an insulating film which is self-alignedly provided around the plate electrode.

    摘要翻译： 公开了一种实现高集成度和高​​可靠性的兆比特动态随机存取存储器。 消除了对制造堆叠式电容器存储单元进行的光掩模对准的允许的需要。 每个存储单元的平板电极通过绝缘膜与存储器阵列中的对应数据线隔离，该绝缘膜自行设置在平板电极周围。