公开(公告)号：US07704854B2

公开(公告)日：2010-04-27

申请号：US12115690

申请日：2008-05-06

申请人： Robert H. Dennard ,  Mark C. Hakey ,  David V. Horak ,  Sanjay Mehta

发明人： Robert H. Dennard ,  Mark C. Hakey ,  David V. Horak ,  Sanjay Mehta

IPC分类号： H01L21/76

CPC分类号： H01L21/76283

摘要： The invention relates to a method includes etching at least one shallow trench in at least an SIO layer; forming a dielectric liner at an interface of the SIO layer and the SIO layer; forming a metal or metal alloy layer in the shallow trench on the dielectric liner; and filling the shallow trench with oxide material over the metal or metal alloy.

摘要翻译： 本发明涉及一种方法，包括在至少一个SIO层中蚀刻至少一个浅沟槽; 在SIO层和SIO层的界面处形成电介质衬垫; 在电介质衬垫上的浅沟槽中形成金属或金属合金层; 并在金属或金属合金上用氧化物填充浅沟槽。

公开(公告)号：US20100076785A1

公开(公告)日：2010-03-25

申请号：US12284929

申请日：2008-09-25

申请人： Sanjay Mehta ,  Debashis Neogi

发明人： Sanjay Mehta ,  Debashis Neogi

IPC分类号： G06Q50/00 ,  G06F17/30

CPC分类号： G06Q50/24 ,  G06F19/328 ,  G06N20/00 ,  G06Q50/22 ,  G16H50/20 ,  G16H50/50 ,  Y02A90/22 ,  Y02A90/26

摘要： Systems and methods are provided for predicting rare events, such as hospitalization events. Data related to health and/or healthcare may be compiled from a number of sources and used to construct a predictive model. The predictive model employ Principal Component Analysis (PCA) and Partial Least Squares (PLS). The data may be arranged in a timeline, and formatted in such a way as to provide discrete temporal “batches”. This arrangement may facilitate the PCA and PLS decomposition of the data into predictive models. These models may then be applied to an individual's data, to create a prediction of healthcare related events.

摘要翻译： 提供系统和方法来预测罕见事件，如住院事件。 与健康和/或保健有关的数据可以从许多来源编制并用于构建预测模型。 预测模型采用主成分分析（PCA）和偏最小二乘法（PLS）。 数据可以以时间线布置，并且以提供离散时间“批次”的方式进行格式化。 这种安排可以促进PCA和PLS将数据分解成预测模型。 然后可以将这些模型应用于个人的数据，以创建与医疗相关事件的预测。

公开(公告)号：US20080090402A1

公开(公告)日：2008-04-17

申请号：US11536893

申请日：2006-09-29

申请人： Griselda Bonilla ,  Shyng-Tsong Chen ,  John A. Fitzsimmons ,  Sanjay Mehta ,  Shom Ponoth

发明人： Griselda Bonilla ,  Shyng-Tsong Chen ,  John A. Fitzsimmons ,  Sanjay Mehta ,  Shom Ponoth

IPC分类号： H01L21/44

CPC分类号： H01L21/76825 ,  H01J2237/0812 ,  H01L21/76883

摘要： A method of fabricating and a structure of an integrated circuit (IC) incorporating a porous dielectric layer are disclosed. A metal line is formed in the porous dielectric layer. A gas cluster ion beam process is applied to the porous dielectric layer so that an upper portion of the dielectric layer is densified to be not porous or non-interconnected low porous, while a lower portion of the porous dielectric layer still maintains its ultra-low dielectric constant after the gas cluster ion beam process.

摘要翻译： 公开了一种制造方法和结合有多孔介电层的集成电路（IC）的结构。 在多孔介电层中形成金属线。 将气体簇离子束工艺应用于多孔介电层，使得电介质层的上部被致密化为不是多孔的或不互连的低多孔，而多孔介电层的下部仍保持其超低 气体离子束过程后的介电常数。

公开(公告)号：US20080012142A1

公开(公告)日：2008-01-17

申请号：US11307642

申请日：2006-02-15

申请人： Sanjay Mehta ,  Daniel Edelstein ,  John Fitzsimmons ,  Stephan Grunow ,  Henry Nye ,  David Rath

发明人： Sanjay Mehta ,  Daniel Edelstein ,  John Fitzsimmons ,  Stephan Grunow ,  Henry Nye ,  David Rath

IPC分类号： H01L23/48 ,  H01L21/4763

CPC分类号： H01L23/5226 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76844 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods are provided that enable the ability to use a less aggressive liner processes, while producing structures known to give a desired high stress migration and electro-migration reliability. The present invention circumvents the issue of sputter damage of low k (on the order of 3.2 or less) dielectric by creating the via “anchors” (interlocked and interpenetrated vias) through chemical means. This allows the elimination or significant reduction of the sputter-etching process used to create the via penetration (“drilling, gouging”) into the line below in the barrier/seed metallization step. The present invention achieves the above, while maintaining a reliable copper fill and device structure.

摘要翻译： 提供了使得能够使用较不积极的衬里工艺的能力，同时产生已知具有期望的高应力迁移和电迁移可靠性的结构。 本发明通过化学方法制造通孔“锚”（互锁和相互穿透的通孔）来规避低k（约3.2以下）电介质的溅射损伤问题。 这允许在阻挡/种子金属化步骤中消除或显着减少用于在下面的线中产生通孔穿透（“钻孔，气刨”）的溅射蚀刻工艺。 本发明实现上述，同时保持可靠的铜填充和装置结构。

公开(公告)号：US20070224824A1

公开(公告)日：2007-09-27

申请号：US11609040

申请日：2006-12-11

申请人： Shyng-Tsong Chen ,  Nancy R. Klymko ,  Anita Madan ,  Sanjay Mehta ,  Steven E. Molis

发明人： Shyng-Tsong Chen ,  Nancy R. Klymko ,  Anita Madan ,  Sanjay Mehta ,  Steven E. Molis

IPC分类号： H01L21/311

CPC分类号： H01L21/3105 ,  H01L21/31155 ,  H01L21/76808 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76831

摘要： When an interconnect structure is built on porous ultra low k (ULK) material, the bottom and/or sidewall of the trench and/or via is usually damaged by a following metallization or cleaning process which may be suitable for dense higher dielectric materials. Embodiments of the present invention may provide a method of repairing process induced dielectric damage from forming an interconnect structure on an inter-layer dielectric (ILD) material. The method includes treating an exposed area of the ILD material to create a carbon-rich area, and metallizing the carbon-rich area. One embodiment includes providing treatment to an exposed sidewall area of the ILD material to create a carbon-rich area by irradiating the exposed area using a gas cluster ion beam (GCIB) generated through a gas including a straight chain or branched, aliphatic or aromatic hydrocarbon, and metallizing the carbon-rich area.

摘要翻译： 当互连结构构建在多孔超低k（ULK）材料上时，沟槽和/或通孔的底部和/或侧壁通常被以下金属化或清洁工艺损坏，这可能适合于较高的介电材料。 本发明的实施例可以提供一种通过在层间电介质（ILD）材料上形成互连结构来修复工艺引起的介电损伤的方法。 该方法包括处理ILD材料的暴露区域以产生富含碳的区域，以及使富含碳的区域金属化。 一个实施例包括通过使用通过包括直链或支链，脂族或芳族烃的气体产生的气体簇离子束（GCIB）照射暴露区域来向ILD材料的暴露的侧壁区域提供处理以产生富碳区域 ，并且富含碳的区域金属化。

公开(公告)号：US20060189133A1

公开(公告)日：2006-08-24

申请号：US11063152

申请日：2005-02-22

申请人： Christos Dimitrakopoulos ,  Stephen Gates ,  Vincent McGahay ,  Sanjay Mehta

发明人： Christos Dimitrakopoulos ,  Stephen Gates ,  Vincent McGahay ,  Sanjay Mehta

IPC分类号： H01L21/4763 ,  H01L21/44 ,  H01L23/48

CPC分类号： H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76885 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates to methods of improving the fabrication of interconnect structures of the single or dual damascene type, in which there is no problem of hard mask retention or of conductivity between the metal lines after fabrication. The methods of the present invention include at least steps of chemical mechanical polishing and UV exposure or chemical repair treatment which steps improve the reliability of the interconnect structure formed. The present invention also relates to an interconnect structure which include a porous ultra low k dielectric of the SiCOH type in which the surface layer thereof has been modified so as to form a gradient layer that has both a density gradient and a C content gradient.

摘要翻译： 本发明涉及改进单镶嵌型或双镶嵌型互连结构的制造方法，其中在制造之后金属线之间没有硬掩模保持或导电性问题。 本发明的方法包括化学机械抛光和紫外线曝光或化学修复处理的至少步骤，这些步骤提高了形成的互连结构的可靠性。 本发明还涉及一种互连结构，其包括SiCOH型的多孔超低k电介质，其中其表面层被修饰以形成具有密度梯度和C含量梯度的梯度层。

公开(公告)号：US09209126B2

公开(公告)日：2015-12-08

申请号：US13606788

申请日：2012-09-07

申请人： Qinghuang Lin ,  Sanjay Mehta ,  Hosadurga Shobha

发明人： Qinghuang Lin ,  Sanjay Mehta ,  Hosadurga Shobha

IPC分类号： H01L23/522 ,  H01L23/532 ,  H01L21/768

CPC分类号： H01L23/5222 ,  H01L21/768 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L23/53295 ,  H01L2221/1026 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure and methods for making the same include sidewall portions of an interlevel dielectric layer. The sidewall portions have a width less than a minimum feature size for a given lithographic technology and the width is formed by a thickness of the interlevel dielectric layer when conformally formed on vertical surfaces of a mandrel. The sidewall portions form spaced-apart openings. Conductive structures fill the spaced-apart openings and are separated by the sidewall portions to form single damascene structures.

摘要翻译： 互连结构及其制造方法包括层间电介质层的侧壁部分。 侧壁部分具有小于给定平版印刷技术的最小特征尺寸的宽度，并且当在心轴的垂直表面上共形形成时，宽度由层间电介质层的厚度形成。 侧壁部分形成间隔开的开口。 导电结构填充间隔开的开口并且被侧壁部分分开以形成单个镶嵌结构。

公开(公告)号：US20130175625A1

公开(公告)日：2013-07-11

申请号：US13622712

申请日：2012-09-19

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Amlan Majumdar ,  Sanjay Mehta

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Amlan Majumdar ,  Sanjay Mehta

IPC分类号： H01L29/78

CPC分类号： H01L21/2255 ,  H01L21/823814 ,  H01L21/84 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66636

摘要： A transistor structure includes a channel located in an extremely thin silicon on insulator (ETSOI) layer and disposed between a raised source and a raised drain, a gate structure having a gate conductor disposed over the channel and between the source and the drain, and a gate spacer layer disposed over the gate conductor. The raised source and the raised drain each have a facet that is upwardly sloping away from the gate structure. A lower portion of the source and a lower portion of the drain are separated from the channel by an extension region containing a dopant species diffused from a dopant-containing glass.

摘要翻译： 晶体管结构包括位于极薄的绝缘体上硅（ETSOI）层上的通道，并且设置在升高的源极和升高的漏极之间的栅极结构，栅极结构具有布置在沟道上方以及源极与漏极之间的栅极结构，以及 栅极间隔层设置在栅极导体上。 升高的源极和升高的漏极各自具有远离栅极结构向上倾斜的小面。 源极的下部和漏极的下部通过包含从含掺杂剂的玻璃扩散的掺杂​​物种的延伸区与沟道分离。

公开(公告)号：US08440552B1

公开(公告)日：2013-05-14

申请号：US13346008

申请日：2012-01-09

申请人： Kangguo Chen ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Amlan Majumdar ,  Sanjay Mehta

发明人： Kangguo Chen ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Amlan Majumdar ,  Sanjay Mehta

IPC分类号： H01L21/225

CPC分类号： H01L21/2255 ,  H01L21/823814 ,  H01L21/84 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66636

摘要： A method includes providing an ETSOI wafer having a semiconductor layer having a top surface with at least one gate structure having on sidewalls thereof a layer of dielectric material. A portion of the layer of dielectric material extends away from the gate structure on the surface of the semiconductor layer. The method further includes faulting a raised S/D on the semiconductor layer adjacent to the portion of the layer of dielectric material, removing the portion of the layer of dielectric material to expose an underlying portion of the surface of the semiconductor layer and applying a layer of glass containing a dopant to cover at least the exposed portion of the surface of the semiconductor layer. The method further includes diffusing the dopant through the exposed portion of the surface of the semiconductor layer to form a source extension region and a drain extension region.

摘要翻译： 一种方法包括提供具有半导体层的ETSOI晶片，所述半导体层具有顶表面，所述半导体层具有至少一个在其侧壁上具有介电材料层的栅极结构。 电介质材料层的一部分远离半导体层表面上的栅极结构延伸。 该方法还包括将邻近该介电材料层的部分的半导体层上的升高的S / D断开，去除介电材料层的该部分以暴露该半导体层表面的下面部分并施加一层 的含有掺杂剂的玻璃以至少覆盖半导体层的表面的暴露部分。 该方法还包括通过半导体层的表面的暴露部分扩散掺杂剂以形成源极延伸区域和漏极延伸区域。

公开(公告)号：US08232179B2

公开(公告)日：2012-07-31

申请号：US12571483

申请日：2009-10-01

申请人： Jason E Cummings ,  Lisa F Edge ,  Balasubramanian S. Haran ,  David V Horak ,  Hemanth Jagannathan ,  Sanjay Mehta

发明人： Jason E Cummings ,  Lisa F Edge ,  Balasubramanian S. Haran ,  David V Horak ,  Hemanth Jagannathan ,  Sanjay Mehta

IPC分类号： H01L21/76

CPC分类号： H01L21/76229

摘要： A method of forming a semiconductor device is provided where in one embodiment an STI fill is recessed below the pad nitride and pad oxide layers, to a level substantially coplanar with the top surface of the substrate. A thin (having a thickness in the range of about 10 Å-100 Å) wet etch resistant layer is formed in contact with and completely covering at least the top surface of the recessed STI fill material. The thin wet etch resistant layer is more resistant to a wet etch process than at least the pad oxide layer. The thin wet etch resistant layer may be a refractory dielectric material, or a dielectric such as HfOx, AlyOx, ZrOx, HfZrOx, and HfSiOx. The inventive wet etch resistant layer improves the wet etch budget of subsequent wet etch processing steps.

摘要翻译： 提供一种形成半导体器件的方法，其中在一个实施例中，STI填充物在衬垫氮化物和衬垫氧化物层下方凹入到与衬底的顶表面基本上共面的水平。 至少形成凹入的STI填充材料的上表面，形成薄（具有在约10埃-120埃范围内的厚度）耐湿蚀刻层。 薄的耐湿蚀刻层比至少衬垫氧化物层更耐湿蚀刻工艺。 薄的耐湿蚀刻层可以是耐火电介质材料，或诸如HfO x，Al y O x，ZrO x，HfZrO x和HfSiO x的电介质。 本发明的耐湿蚀刻层提高了后续湿蚀刻处理步骤的湿法蚀刻预算。