公开(公告)号：US09755038B2

公开(公告)日：2017-09-05

申请号：US15146562

申请日：2016-05-04

Applicant: Acorn Technologies, Inc.

Inventor： Walter A. Harrison ,  Paul A. Clifton ,  Andreas Goebel ,  R. Stockton Gaines

IPC: H01L29/47 ,  H01L21/285 ,  H01L29/04 ,  H01L21/283 ,  H01L29/45 ,  H01L21/324 ,  H01L29/161

CPC classification number: H01L29/47 ,  H01L21/283 ,  H01L21/28512 ,  H01L21/28518 ,  H01L21/324 ,  H01L29/045 ,  H01L29/161 ,  H01L29/456

Abstract: Techniques for reducing the specific contact resistance of metal-semiconductor (group IV) junctions by interposing a monolayer of group V or group III atoms at the interface between the metal and the semiconductor, or interposing a bi-layer made of one monolayer of each, or interposing multiple such bi-layers. The resulting low specific resistance metal-group IV semiconductor junctions find application as a low resistance electrode in semiconductor devices including electronic devices (e.g., transistors, diodes, etc.) and optoelectronic devices (e.g., lasers, solar cells, photodetectors, etc.) and/or as a metal source and/or drain region (or a portion thereof) in a field effect transistor (FET). The monolayers of group III and group V atoms are predominantly ordered layers of atoms formed on the surface of the group IV semiconductor and chemically bonded to the surface atoms of the group IV semiconductor.

公开(公告)号：US09484426B2

公开(公告)日：2016-11-01

申请号：US15043035

申请日：2016-02-12

Applicant: Acorn Technologies, Inc.

Inventor： Walter A. Harrison ,  Paul A. Clifton ,  Andreas Goebel ,  R. Stockton Gaines

IPC: H01L29/47

CPC classification number: H01L29/47 ,  H01L21/283 ,  H01L21/28512 ,  H01L21/28518 ,  H01L21/324 ,  H01L29/045 ,  H01L29/161 ,  H01L29/456

Abstract: Techniques for reducing the specific contact resistance of metal-semiconductor (group IV) junctions by interposing a monolayer of group V or group III atoms at the interface between the metal and the semiconductor, or interposing a bi-layer made of one monolayer of each, or interposing multiple such bi-layers. The resulting low specific resistance metal—group IV semiconductor junctions find application as a low resistance electrode in semiconductor devices including electronic devices (e.g., transistors, diodes, etc.) and optoelectronic devices (e.g., lasers, solar cells, photodetectors, etc.) and/or as a metal source and/or drain region (or a portion thereof) in a field effect transistor (FET). The monolayers of group III and group V atoms are predominantly ordered layers of atoms formed on the surface of the group IV semiconductor and chemically bonded to the surface atoms of the group IV semiconductor.

Abstract translation: 通过在金属和半导体之间的界面处插入V族或III族原子的单层或者插入由每个单层单层制成的双层来降低金属 - 半导体（IV族）结的特定接触电阻的技术， 或插入多个这样的双层。 所得到的低比电阻金属组IV半导体结可用作包括电子器件（例如，晶体管，二极管等）和光电器件（例如，激光器，太阳能电池，光电检测器等）的半导体器件中的低电阻电极， 和/或作为场效应晶体管（FET）中的金属源极和/或漏极区域（或其一部分）。 III族和V族原子的单层主要是在IV族半导体的表面上形成的化学键合到IV族半导体的表面原子上的原子的有序层。

公开(公告)号：US09461167B2

公开(公告)日：2016-10-04

申请号：US15048893

申请日：2016-02-19

Applicant: Acorn Technologies, Inc.

Inventor： Daniel E. Grupp ,  Daniel J. Connelly

IPC: H01L29/78 ,  H01L29/872 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66 ,  H01L29/80

CPC classification number: H01L29/456 ,  H01L21/28537 ,  H01L29/0895 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/45 ,  H01L29/47 ,  H01L29/66143 ,  H01L29/66643 ,  H01L29/78 ,  H01L29/7839 ,  H01L29/785 ,  H01L29/806 ,  H01L29/812 ,  H01L29/872

Abstract: An electrical device in which an interface layer is disposed in between and in contact with a conductor and a semiconductor.

Abstract translation: 一种电气装置，其中界面层设置在导体和半导体之间并与导体和半导体接触。

公开(公告)号：US20150333933A1

公开(公告)日：2015-11-19

申请号：US14276857

申请日：2014-05-13

Applicant: Acorn Technologies, Inc.

Inventor： Fernando Lopez de Victoria

IPC: H04L25/02

CPC classification number: H04L25/0212 ,  H04L25/021 ,  H04L25/0224 ,  H04L25/0232 ,  H04L25/025 ,  H04L25/03159 ,  H04L2025/03713

Abstract: An OFDM system generates a channel estimate in the time domain for use in either a frequency domain equalizer or in a time domain equalizer. Preferably channel estimation is accomplished in the time domain using a locally generated reference signal. The channel estimator generates an initial estimate from a cross correlation between the time domain reference signal and an input signal input to the receiver and generates at least one successive channel estimate. Preferably the successive channel estimate is determined by vector addition (or subtraction) to the initial channel estimate. The at least one successive channel estimate reduces the minimum mean square error of the estimate with respect to a received signal.

Abstract translation: OFDM系统在时域中产生用于频域均衡器或时域均衡器中的信道估计。 优选地，使用本地生成的参考信号在时域中完成信道估计。 信道估计器根据时域参考信号和输入到接收机的输入信号之间的互相关产生初始估计，并产生至少一个连续的信道估计。 优选地，通过对初始信道估计的向量相加（或减法）来确定连续信道估计。 所述至少一个连续的信道估计相对于接收到的信号减小估计的最小均方误差。

公开(公告)号：US09059201B2

公开(公告)日：2015-06-16

申请号：US13742067

申请日：2013-01-15

Applicant: Paul A. Clifton

Inventor： Paul A. Clifton

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/84

CPC classification number: H01L29/66477 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/1054 ,  H01L29/78

Abstract: Processes for making field effect transistors relax a buried stressor layer to induce strain in a silicon surface layer above the buried stressor layer. The buried stressor layer is relaxed and the surface layer is strained by implantation into at least the buried stressor layer, preferably on both sides of a portion of the surface layer that is to be stressed. For example, implanting ions through the surface silicon layer on either side of the gate structure of the preferred FET implementation into an underlying stressor layer can induce strain in a channel region of the FET. This process can begin with a silicon or silicon-on-insulator substrate with a buried silicon germanium layer having an appropriate thickness and germanium concentration. Other stressor materials can be used.

Abstract translation: 用于制造场效应晶体管的过程放松埋置的应力层以在埋层应力层上方的硅表面层中引起应变。 埋置的应力层松弛，并且表面层通过注入到至少埋置的应力层中，优选地在被压应的表面层的一部分的两侧被应变。 例如，通过优选FET实施方式的栅极结构的任一侧的表面硅层将离子注入到下面的应力层中可以在FET的沟道区域中引起应变。 该工艺可以以具有适当厚度和锗浓度的掩埋硅锗层的硅或绝缘体上硅衬底开始。 可以使用其他应力源材料。

公开(公告)号：US20140369372A1

公开(公告)日：2014-12-18

申请号：US14256758

申请日：2014-04-18

Applicant: Acorn Technologies, Inc.

Inventor： Paul A. Clifton ,  Andreas Goebel ,  R. Stockton Gaines

IPC: H01S5/32 ,  H01S5/125 ,  H01S5/187

CPC classification number: H01S5/187 ,  B82Y20/00 ,  H01L27/14625 ,  H01L27/14643 ,  H01L31/028 ,  H01L31/0352 ,  H01L31/1808 ,  H01L33/34 ,  H01S5/125 ,  H01S5/2203 ,  H01S5/227 ,  H01S5/3201 ,  H01S5/3223 ,  H01S5/3224 ,  H01S5/3427 ,  Y02E10/547

Abstract: Tensile strained germanium is provided that can be sufficiently strained to provide a nearly direct band gap material or a direct band gap material. Compressively stressed or tensile stressed stressor materials in contact with germanium regions induce uniaxial or biaxial tensile strain in the germanium regions. Stressor materials may include silicon nitride or silicon germanium. The resulting strained germanium structure can be used to emit or detect photons including, for example, generating photons within a resonant cavity to provide a laser.

Abstract translation: 提供拉伸应变锗，其可以被充分应变以提供几乎直接的带隙材料或直接带隙材料。 与锗区接触的压应力或拉应力应力源材料在锗区域引起单轴或双轴拉伸应变。 应力材料可以包括氮化硅或硅锗。 所得到的应变锗结构可用于发射或检测光子，包括例如在谐振腔内产生光子以提供激光。

公开(公告)号：US20140225160A1

公开(公告)日：2014-08-14

申请号：US13762677

申请日：2013-02-08

Applicant: Paul A. Clifton ,  R Stockton Gaines

Inventor： Paul A. Clifton ,  R Stockton Gaines

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7849 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/7624 ,  H01L21/76251 ,  H01L21/76254 ,  H01L21/76283 ,  H01L21/823412 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/105 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66477 ,  H01L29/66568 ,  H01L29/66742 ,  H01L29/7838 ,  H01L29/7846 ,  H01L29/78603

Abstract: An SOI wafer contains a compressively stressed buried insulator structure. In one example, the stressed buried insulator (BOX) may be formed on a host wafer by forming silicon oxide, silicon nitride and silicon oxide layers so that the silicon nitride layer is compressively stressed. Wafer bonding provides the surface silicon layer over the stressed insulator layer. Preferred implementations of the invention form MOS transistors by etching isolation trenches into a preferred SOI substrate having a stressed BOX structure to define transistor active areas on the surface of the SOI substrate. Most preferably the trenches are formed deep enough to penetrate through the stressed BOX structure and some distance into the underlying silicon portion of the substrate. The overlying silicon active regions will have tensile stress induced due to elastic edge relaxation.

Abstract translation: SOI晶片包含压应力埋层绝缘体结构。 在一个示例中，应力埋层绝缘体（BOX）可以通过形成氧化硅，氮化硅和氧化硅层而形成在主晶片上，使得氮化硅层受到压应力。 晶片接合在应力绝缘体层上提供表面硅层。 本发明的优选实施方案通过将隔离沟槽蚀刻到具有应力BOX结构的优选SOI衬底中来形成MOS晶体管，以在SOI衬底的表面上限定晶体管有源区。 最优选地，沟槽形成得足够深以穿过受压的BOX结构并且进入到衬底的下面的硅部分的一些距离。 覆盖的硅有源区域将由于弹性边缘松弛而产生拉伸应力。

公开(公告)号：US08658523B2

公开(公告)日：2014-02-25

申请号：US12878930

申请日：2010-09-09

Applicant: Carl M. Faulkner ,  Daniel J. Connelly ,  Paul A. Clifton ,  Daniel E. Grupp

Inventor： Carl M. Faulkner ,  Daniel J. Connelly ,  Paul A. Clifton ,  Daniel E. Grupp

IPC: H01L21/28

CPC classification number: H01L21/28537 ,  H01L27/1203 ,  H01L29/161 ,  H01L29/41733 ,  H01L29/458 ,  H01L29/47 ,  H01L29/66636 ,  H01L29/66643 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7839 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78645 ,  H01L29/78654 ,  H01L29/78681 ,  H01L29/78684

Abstract: A metal source/drain field effect transistor is fabricated such that the source/drain regions are deposited, multilayer structures, with at least a second metal deposited on exposed surfaces of a first metal.

Abstract translation: 制造金属源极/漏极场效应晶体管，使得源极/漏极区域被沉积，多层结构，至少第二金属沉积在第一金属的暴露表面上。

公开(公告)号：US20130140629A1

公开(公告)日：2013-06-06

申请号：US13757597

申请日：2013-02-01

Applicant: Acorn Technologies, Inc.

Inventor： Daniel E. Grupp ,  Daniel J. Connelly

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/47 ,  H01L21/28537 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/0895 ,  H01L29/456 ,  H01L29/4908 ,  H01L29/66143 ,  H01L29/66636 ,  H01L29/66643 ,  H01L29/66666 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/66848 ,  H01L29/78 ,  H01L29/7827 ,  H01L29/7839 ,  H01L29/785 ,  H01L29/78696 ,  H01L29/812 ,  H01L29/8126 ,  Y10S438/958

Abstract: A transistor having at least one passivated Schottky barrier to a channel includes an insulated gate structure on a p-type substrate in which the channel is located beneath the insulated gate structure. The channel and the insulated gate structure define a first and second undercut void regions that extend underneath the insulated gate structure toward the channel from a first and a second side of the insulated gate structure, respectively. A passivation layer is included on at least one exposed sidewall surface of the channel, and metal source and drain terminals are located on respective first and second sides of the channel, including on the passivation layer and within the undercut void regions beneath the insulated gate structure. At least one of the metal source and drain terminals comprises a metal that has a work function near a valence band of the p-type substrate.

Abstract translation: 具有至少一个通道的钝化肖特基势垒的晶体管包括在p型衬底上的绝缘栅极结构，其中沟道位于绝缘栅极结构之下。 通道和绝缘栅极结构分别限定了从绝缘栅极结构的第一和第二侧分别延伸到绝缘栅极结构下方朝向沟道的第一和第二底切空隙区域。 钝化层包括在通道的至少一个暴露的侧壁表面上，并且金属源极和漏极端子位于通道的相应的第一和第二侧上，包括在钝化层上以及绝缘栅极结构下面的底切空隙区域 。 金属源极和漏极端子中的至少一个包括在p型衬底的价带附近具有功函数的金属。

公开(公告)号：US08450133B2

公开(公告)日：2013-05-28

申请号：US12404782

申请日：2009-03-16

Applicant: Paul A. Clifton

Inventor： Paul A. Clifton

IPC: H01L21/00

CPC classification number: H01L31/068 ,  H01L31/028 ,  H01L31/0304 ,  H01L31/035281 ,  H01L31/0687 ,  H01L31/07 ,  H01L31/103 ,  H01L31/107 ,  H01L31/109 ,  H01L31/1804 ,  H01L31/1808 ,  H01L31/184 ,  Y02E10/544 ,  Y02E10/547 ,  Y02P70/521

Abstract: Improved silicon solar cells, silicon image sensors and like photosensitive devices are made to include strained silicon at or sufficiently near the junctions or other active regions of the devices to provide increased sensitivity to longer wavelength light. Strained silicon has a lower band gap than conventional silicon. One method of making a solar cell that contains tensile strained silicon etches a set of parallel trenches into a silicon wafer and induces tensile strain in the silicon fins between the trenches. The method may induce tensile strain in the silicon fins by filling the trenches with compressively strained silicon nitride or silicon oxide. A deposited layer of compressively strained silicon nitride adheres to the walls of the trenches and generates biaxial tensile strain in the plane of adjacent silicon fins.

Abstract translation: 改进的硅太阳能电池，硅图像传感器和类似的光敏器件被制成包括在器件的结或其他有源区处或足够靠近的应变硅以提供对较长波长光的增强的灵敏度。 应变硅具有比常规硅更低的带隙。 制造包含拉伸应变硅的太阳能电池的一种方法将一组平行的沟槽蚀刻成硅晶片并且在沟槽之间的硅散热片中引起拉伸应变。 该方法可以通过用压缩应变的氮化硅或氧化硅填充沟槽来引起硅散热片中的拉伸应变。 压缩应变氮化硅的沉积层粘附到沟槽的壁上并在相邻的硅散热片的平面中产生双轴拉伸应变。