公开(公告)号：US20230378295A1

公开(公告)日：2023-11-23

申请号：US18197909

申请日：2023-05-16

申请人： STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS

发明人： Siddhartha DHAR ,  Stephane MONFRAY ,  Alain FLEURY ,  Franck JULIEN

IPC分类号： H01L29/423 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/40

CPC分类号： H01L29/42368 ,  H01L27/088 ,  H01L21/823462 ,  H01L29/401

摘要： A transistor includes a semiconductor layer with a stack of a gate insulator and a conductive gate on the semiconductor layer. A thickness of the gate insulator is variable in a length direction of the transistor. The gate insulator includes a first region having a first thickness below a central region of the conductive gate. The gate insulator further includes a second region having a second thickness, greater than the first thickness, below an edge region of conductive gate.

公开(公告)号：US20230361187A1

公开(公告)日：2023-11-09

申请号：US17935616

申请日：2022-09-27

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC. ,  CHANGXIN JIDIAN (BEIJING) MEMORY TECHNOLOGIES CO., LTD.

发明人： Zhaohong LV

IPC分类号： H01L29/423 ,  H01L29/78 ,  H01L29/51 ,  H01L29/66

CPC分类号： H01L29/42368 ,  H01L29/7836 ,  H01L29/512 ,  H01L29/6659 ,  H01L29/518

摘要： The present disclosure relates to the technical field of semiconductors, and provides a manufacturing method of a semiconductor structure and a semiconductor structure. The substrate comprises an active region, and the active region is provided with a source region of a first doping type and a drain region of the first doping type; the first dielectric layer is at least partially provided on the substrate and covers a part of the source region and/or a part of the drain region; the second dielectric layer is provided on the substrate, the first dielectric layer is connected to the second dielectric layer, and a thickness of the second dielectric layer is less than a thickness of the first dielectric layer; orthographic projection of the gate structure on the substrate covers orthographic projection of the second dielectric layer and orthographic projection of the first dielectric layer on the substrate.

公开(公告)号：US11791396B2

公开(公告)日：2023-10-17

申请号：US17371714

申请日：2021-07-09

申请人： International Business Machines Corporation

发明人： Kangguo Cheng ,  Ruilong Xie ,  Julien Frougier ,  Chanro Park

IPC分类号： H01L29/66 ,  H01L29/423

CPC分类号： H01L29/66484 ,  H01L29/42368 ,  H01L29/66545 ,  H01L29/66553

摘要： A multiple gate dielectrics and dual work-functions field effect transistor (MGO-DWF-FET) is provided on an active region of a semiconductor substrate. The MGO-DWF-FET includes a first functional gate structure including a U-shaped first high-k gate dielectric material layer and a first work-function metal-containing structure, and a laterally adjacent, and contacting, second functional gate structure that includes a U-shaped second high-k gate dielectric material layer and a second work-function metal-containing structure. The first functional gate structure has a gate length that differs from a gate length of the second functional gate structure.

公开(公告)号：US11791390B2

公开(公告)日：2023-10-17

申请号：US17530275

申请日：2021-11-18

申请人： SK hynix Inc.

发明人： Se-Han Kwon ,  Dong-Soo Kim

IPC分类号： H01L29/49 ,  H01L29/423 ,  H01L21/3213 ,  H01L21/02 ,  H01L21/67 ,  H01L21/28 ,  H01L21/3105 ,  H10B12/00

CPC分类号： H01L29/4236 ,  H01L21/0217 ,  H01L21/28088 ,  H01L21/31056 ,  H01L21/32136 ,  H01L21/67075 ,  H01L29/4238 ,  H01L29/42368 ,  H01L29/4966 ,  H01L29/4991 ,  H10B12/053 ,  H10B12/34

摘要： Disclosed is a semiconductor device for improving a gate induced drain leakage and a method for fabricating the same, and the method may include forming a trench in a substrate, lining a surface of the trench with an initial gate dielectric layer, forming a gate electrode to partially fill the lined trench, forming a sacrificial material spaced apart from a top surface of the gate electrode and to selectively cover a top corner of the lined trench, removing a part of the initial gate dielectric layer of the lined trench which is exposed by the sacrificial material in order to form an air gap, and forming a capping layer to cap a side surface of the air gap, over the gate electrode.

公开(公告)号：US11769542B2

公开(公告)日：2023-09-26

申请号：US17501464

申请日：2021-10-14

申请人： Micron Technology, Inc.

发明人： Kamal M. Karda ,  Chandra Mouli ,  Durai Vishak Nirmal Ramaswamy ,  F. Daniel Gealy

IPC分类号： G11C11/22 ,  H01L29/788 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H10B51/30

CPC分类号： G11C11/223 ,  H01L29/4234 ,  H01L29/42324 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/6684 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7887 ,  H01L29/7889 ,  H01L29/78391 ,  H10B51/30

摘要： A field effect transistor construction includes a semiconductive channel core. A source/drain region is at opposite ends of the channel core. A gate is proximate a periphery of the channel core. A gate insulator is between the gate and the channel core. The gate insulator has local regions radially there-through that have different capacitance at different circumferential locations relative to the channel core periphery. Additional constructions, and methods, are disclosed.

公开(公告)号：US11757028B2

公开(公告)日：2023-09-12

申请号：US17559148

申请日：2021-12-22

申请人： KABUSHIKI KAISHA TOSHIBA ,  TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION

发明人： Yosuke Kajiwara ,  Daimotsu Kato ,  Masahiko Kuraguchi

IPC分类号： H01L29/778 ,  H01L21/02 ,  H01L21/28 ,  H01L29/423 ,  H01L29/205 ,  H01L29/20 ,  H01L29/51 ,  H01L29/66

CPC分类号： H01L29/7787 ,  H01L21/02458 ,  H01L21/28264 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42356 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66462 ,  H01L21/02241 ,  H01L21/02326

摘要： According to one embodiment, a semiconductor device includes first to third electrodes, first and second semiconductor layers, a nitride layer, and an oxide layer. A direction from the second electrode toward the first electrode is aligned with a first direction. A position in the first direction of the third electrode is between the first electrode and the second electrode in the first direction. The first semiconductor layer includes first to fifth partial regions. The first partial region is between the fourth and third partial regions in the first direction. The second partial region is between the third and fifth partial regions in the first direction. The nitride layer includes first and second nitride regions. The second semiconductor layer includes first and second semiconductor regions. The oxide layer includes silicon and oxygen. The oxide layer includes first to third oxide regions.

公开(公告)号：US20230282721A1

公开(公告)日：2023-09-07

申请号：US18006622

申请日：2021-05-26

申请人： SONY SEMICONDUCTOR SOLUTIONS CORPORATION

发明人： YUKI YANAGISAWA ,  KATSUHIKO TAKEUCHI

IPC分类号： H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/778 ,  H01L29/40

CPC分类号： H01L29/42368 ,  H01L29/401 ,  H01L29/42376 ,  H01L29/512 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/2003

摘要： Fluctuation and deterioration of characteristics of a semiconductor device are reduced. The semiconductor device includes a field effect transistor mounted on a semiconductor base. In addition, the field effect transistor includes an insulation layer that includes a first insulation film provided on a main surface of the semiconductor base, and a second insulation film provided on the first insulation film and having etching selectivity higher than etching selectivity of the first insulation film, a gate electrode that has a head part located on the insulation layer and a body part extending from the head part toward the main surface of the semiconductor base and is configured such that the head part has a width larger than a width of the body part, and an embedded film provided between the first insulation film and the body part of the gate electrode in a gate length direction of the gate electrode, and having a relative permittivity equal to or higher than a relative permittivity of the second insulation film.

公开(公告)号：US20230261104A1

公开(公告)日：2023-08-17

申请号：US17669831

申请日：2022-02-11

申请人： Infineon Technologies Austria AG

发明人： Adrian Finney ,  Harsh Naik ,  Ingmar Neumann

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/40 ,  H01L29/423

CPC分类号： H01L29/7813 ,  H01L29/7811 ,  H01L29/66734 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/401

摘要： A semiconductor device includes: a semiconductor substrate; a drift zone of a first conductivity type in the semiconductor substrate; an array of interconnected gate trenches extending from a first surface of the semiconductor substrate into the drift zone; a plurality of semiconductor mesas delimited by the array of interconnected gate trenches; a plurality of needle-shaped field plate trenches extending from the first surface into the plurality of semiconductor mesas; in the plurality of semiconductor mesas, a source region of the first conductivity type and a body region of a second conductivity type separating the source region from the drift zone; and a current spreading region of the first conductivity type at the bottom of the gate trenches and having a higher average doping concentration than the drift zone. Methods of producing the semiconductor device are also described.

公开(公告)号：US20230246104A1

公开(公告)日：2023-08-03

申请号：US18152881

申请日：2023-01-11

申请人： NEXPERIA B.V.

发明人： Steven Peake

IPC分类号： H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06

CPC分类号： H01L29/7813 ,  H01L29/0696 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66734

摘要： A Metal Oxide Semiconductor (MOS), Field Effect Transistor (FET), (MOSFET) is provided, including a semiconductor body having a first major surface, and two trenches extending in the semiconductor body from the first major surface, a source region of a first conductivity type adjacent sidewalls of the two trenches at the first major surface, a drain region of the first conductivity type adjacent the two trenches at a position distant from the source region, a channel-accommodating region, of a second conductivity type opposite to the first conductivity type, adjacent the sidewalls of the two trenches between the source region and the drain region, and a first of the two trenches extends further into the semiconductor body compared to a second of the two trenches.

公开(公告)号：US11695060B2

公开(公告)日：2023-07-04

申请号：US17127298

申请日：2020-12-18

申请人： Applied Materials, Inc.

发明人： Qintao Zhang ,  Samphy Hong ,  Wei Zou ,  Lei Zhong ,  David J. Lee ,  Felix Levitov

IPC分类号： H01L21/04 ,  H01L21/28 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423

CPC分类号： H01L29/66734 ,  H01L21/2822 ,  H01L29/42368

摘要： Disclosed herein are methods for forming MOSFETs. In some embodiments, a method may include providing a device structure including a plurality of trenches, and forming a mask over the device structure including within each of the plurality of trenches and over a top surface of the device structure. The method may further include removing the mask from within the trenches, wherein the mask remains along the top surface of the device structure, and implanting the device structure to form a treated layer along a bottom of the trenches. In some embodiments, the method may further include forming a gate oxide layer along a sidewall of each of the trenches and along the bottom of the trenches, wherein a thickness of the oxide along the bottom of the trenches is greater than a thickness of the oxide along the sidewall of each of the trenches.