公开(公告)号：US20240321882A1

公开(公告)日：2024-09-26

申请号：US18189411

申请日：2023-03-24

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Soon-Cheon Seo ,  Ruqiang Bao ,  Min Gyu Sung

IPC分类号： H01L27/092 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/775

CPC分类号： H01L27/092 ,  H01L21/28088 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775

摘要： Within a replacement gate structure, there a first channel cell that includes one or more first channels that are associated with a first transistor device (e.g., a nFET transistor) and a second channel cell that includes one or more second channels that are associated with a second transistor device (e.g., a pFET transistor). A first work function (WF) gate is around the one or more first channels and a second WF gate is around the one or more second channels. In alternative implementations, the replacement gate structure may include separate instances of a replacement gate upon the first WF gate and upon the second WF gate or a shared replacement gate upon both the first WF gate and upon the second WF gate. A gate contact may contact the shared replacement gate or may contact both instances of the replacement gate.

公开(公告)号：US20240321861A1

公开(公告)日：2024-09-26

申请号：US18189482

申请日：2023-03-24

申请人： QUALCOMM Incorporated

发明人： Haining Yang ,  Hyunwoo Park ,  Ming-Huei Lin ,  Junjing Bao

IPC分类号： H01L27/02 ,  H01L27/118 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC分类号： H01L27/0207 ,  H01L27/11807 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

摘要： A logic circuit includes a first circuit having a first diffusion region and a second diffusion region and a second circuit having a third diffusion region, and a fourth diffusion region. First devices in the first circuit each include a portion of the first diffusion region and a portion of the second diffusion region. Second devices in the second circuit each include portions of the third and fourth diffusion regions. The first diffusion region is between the second diffusion region and the third diffusion region. The third diffusion region is between the first diffusion region and the fourth diffusion region. A second distance from a first side of the fourth diffusion region to a second side of the third diffusion region is less than a first distance from a first side of the first diffusion region to a second side of the second diffusion region.

公开(公告)号：US20240321747A1

公开(公告)日：2024-09-26

申请号：US18123613

申请日：2023-03-20

申请人： International Business Machines Corporation

发明人： Ruilong Xie ,  Christopher J. Penny ,  Kisik Choi ,  Koichi Motoyama ,  Nicholas Anthony Lanzillo ,  Chih-Chao Yang

IPC分类号： H01L23/528 ,  H01L21/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC分类号： H01L23/5286 ,  H01L21/7806 ,  H01L21/823807 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

摘要： A semiconductor structure is provided that includes a plurality of backside power islands, rather than backside power rails. The backside power islands are present in a first device track and a second device track. Each backside power island located in the first device track and the second device track are isolated by a first cut region, and the backside power islands that are located in the first device track are separated from the backside power islands located in the second device track by a second cut region. The second cut region is oriented perpendicular to the first cut region.

公开(公告)号：US20240321687A1

公开(公告)日：2024-09-26

申请号：US18186236

申请日：2023-03-20

申请人： International Business Machines Corporation

发明人： Ruilong Xie ,  Nicholas Anthony Lanzillo ,  Lawrence A. Clevenger ,  Huai Huang ,  Hosadurga Shobha

IPC分类号： H01L23/48 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786 ,  H01L29/94

CPC分类号： H01L23/481 ,  H01L21/823807 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696 ,  H01L29/945

摘要： Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. First and second FETs are formed. A top surface of the semiconductor structure is bonded to a carrier wafer. The semiconductor structure is flipped. A MIM capacitor plane comprising first and second metal layers is formed. An ILD layer is formed on the MIM capacitor plane. A first trench is formed within the MIM capacitor plane and the ILD layer. Exposed portions of the first metal layer are recessed within the first trench. A second trench is formed within the MIM capacitor plane and the ILD layer. Exposed portions of the second metal layer are recessed. Dielectric spacers are formed in the recesses. A first backside contact is formed in the first trench and a second backside contact is formed in the second trench.

公开(公告)号：US20240313098A1

公开(公告)日：2024-09-19

申请号：US18598735

申请日：2024-03-07

申请人： Micron Technology, Inc.

发明人： James Brian Johnson ,  Brent Keeth ,  Kunal R. Parekh ,  Eiichi Nakano ,  Amy Rae Griffin

IPC分类号： H01L29/775 ,  H01L23/00 ,  H01L25/065 ,  H01L27/088 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H10B12/00

CPC分类号： H01L29/775 ,  H01L24/80 ,  H01L25/0657 ,  H01L27/0886 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/78696 ,  H01L2224/80895 ,  H01L2924/1436 ,  H10B12/01

摘要： Methods, systems, and devices for transistor architectures in coupled semiconductor systems are described. A memory system may be formed from multiple semiconductor components (e.g., multiple dies, multiple wafers) that are coupled together, with different semiconductor components implementing different techniques for transistor formation. For example, a first die may include a memory array and first circuitry configured to access the memory array, and a second die coupled with the first die may include second circuitry configured to access the memory array. The first circuitry may include transistors formed in accordance with a first fabrication technique (e.g., to form a first type of transistors) and the second circuitry may include transistors formed in accordance with a second fabrication technique (e.g., to form a second type of transistors). The dies may be coupled in a manner that provides an electrical coupling between the first circuitry and the second circuitry.

公开(公告)号：US20240313097A1

公开(公告)日：2024-09-19

申请号：US18513740

申请日：2023-11-20

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： JUNGGIL YANG ,  TAEHYUN KIM ,  TAEWON HA

IPC分类号： H01L29/775 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66

CPC分类号： H01L29/775 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66553

摘要： Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device includes a substrate including a first region and a second region; an active region on the first region and a peripheral active region on the second region; a channel pattern on the active region; a peripheral channel pattern on the peripheral active region; a first gate electrode on the channel pattern; and a second gate electrode on the peripheral channel pattern. A linewidth of the second gate electrode is larger than a linewidth of the first gate electrode, and a difference in height between the first and second gate electrodes is smaller than about 10 nm, and a top surface of the second gate electrode has a doubly-concave shape.

公开(公告)号：US20240313077A1

公开(公告)日：2024-09-19

申请号：US18537536

申请日：2023-12-12

申请人： Samsung Electronics Co., Ltd.

发明人： Chulsung KIM ,  Yeonghan GWON ,  Jinkyung SON ,  Jaepo LIM

IPC分类号： H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L29/775

CPC分类号： H01L29/42392 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/41733 ,  H01L29/66439 ,  H01L29/775

摘要： Disclosed is a semiconductor device comprising a substrate including an active pattern, a channel pattern on the active pattern and including semiconductor patterns that are vertically stacked and spaced apart from each other, a source/drain pattern connected to the semiconductor patterns, a gate electrode on the semiconductor patterns and including inner electrodes between neighboring semiconductor patterns and an outer electrode on an uppermost semiconductor pattern, and a capping pattern on a top surface of the outer electrode. A line-width of the outer electrode is a first width. The outer electrode has a first height. The first height is equal to or less than the first width.

公开(公告)号：US20240312993A1

公开(公告)日：2024-09-19

申请号：US18354515

申请日：2023-07-18

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chung-Wei HSU ,  Lung-Kun CHU ,  Jia-Ni YU ,  Chun-Fu LU ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG

IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC分类号： H01L27/092 ,  H01L21/823807 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

摘要： An integrated circuit includes an NMOS gate all around (GAA) transistor and a PMOS GAA transistor. A single gate metal is utilized for both transistors. An effective work function is imparted to the NMOS transistor by including a first layer of the gate metal around the channels, a semiconductor layer around the first layer of the gate metal, and a gate fill layer of the gate metal on the semiconductor layer. The PMOS transistor, the gate fill layer of the gate metal is on the gate dielectric without an intervening semiconductor layer.

公开(公告)号：US20240312979A1

公开(公告)日：2024-09-19

申请号：US18365483

申请日：2023-08-04

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tao-Yi Hung ,  Wun-Jie Lin ,  Jam-Wem Lee ,  Kuo-Ji Chen

IPC分类号： H01L27/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC分类号： H01L27/0255 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

摘要： A diode structure includes a silicon remaining layer, a first p-type doping region disposed on the silicon remaining layer and a first n-type doping region disposed on the silicon remaining layer. A first channel region is disposed on the silicon remaining layer and between the p-type doping region and the n-type doping region, wherein the first channel region, the first p-type doping region, and the first n-type doping region are disposed along a first direction.

公开(公告)号：US20240304667A1

公开(公告)日：2024-09-12

申请号：US18179519

申请日：2023-03-07

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Huang-Lin Chao ,  Shen-Yang Lee ,  Hsiang-Pi Chang

IPC分类号： H01L29/06 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC分类号： H01L29/0673 ,  H01L29/42392 ,  H01L29/517 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

摘要： A method for fabricating a semiconductor device is disclosed. The method includes exposing one or more surfaces of a conduction channel of a transistor, overlaying the one or more surfaces with a first high-k dielectric layer; overlaying the first high-k dielectric layer with a second high-k dielectric layer; depositing a ruthenium-containing layer over the second high-k dielectric layer; and performing a first annealing process with a temperature not greater than a threshold so as to remove oxygen vacancies from at least the first high-k dielectric layer.