公开(公告)号：US5523703A

公开(公告)日：1996-06-04

申请号：US298047

申请日：1994-08-30

申请人： Kanta Yamamoto ,  Katsuichi Ohara

发明人： Kanta Yamamoto ,  Katsuichi Ohara

IPC分类号： H03K19/086 ,  G06F12/00 ,  G06F13/16 ,  G11C11/401 ,  H03K19/0175 ,  H04B3/02 ,  H04L5/14 ,  H04L12/40 ,  H04L25/02 ,  H03K17/16

CPC分类号： H04L12/40039 ,  H04L12/407 ,  H04L25/0298 ,  H04L5/14

摘要： A method of controlling termination of current driven circuits that bidirectionally transmit and receive a current driven signal, has the step of transmitting the current driven signal from a first one of the current driven circuits and receiving the signal by a second one of at least one of the current driven circuits while connecting only a termination circuit on the receiver side and disconnecting the other termination circuits. Therefore, the method of controlling termination of current driven circuits carries out simple termination switching control to prevent a decrease in the impedance of the output stage of the current driven circuit and transmit the current driven signal at correct amplitude.

摘要翻译： 控制双向传输和接收电流驱动信号的电流驱动电路的终止的方法具有从当前驱动电路中的第一个驱动电路传输当前驱动信号并通过以下至少一个接收信号的步骤： 电流驱动电路，同时仅连接接收器侧的终端电路，并断开其他终端电路。 因此，控制电流驱动电路的终止的方法进行简单的终止切换控制，以防止电流驱动电路的输出级的阻抗减小，并以正确的幅度传输电流驱动信号。

公开(公告)号：US5514984A

公开(公告)日：1996-05-07

申请号：US324500

申请日：1994-10-18

申请人： Satoshi Nakamura

发明人： Satoshi Nakamura

IPC分类号： H03K19/086 ,  H03K17/60 ,  H03K19/013

CPC分类号： H03K19/0136

摘要： In an active pull down ECL apparatus including a current switch formed by an input transistor and a reference transistor, an emitter follower controlled by a collector voltage of the input transistor or the reference transistor, and an active pull down circuit connected to the emitter follower, a resistor is connected to an emitter of the input transistor or the reference transistor.

摘要翻译： 在包括由输入晶体管和参考晶体管形成的电流开关的有源下拉ECL装置中，由输入晶体管或参考晶体管的集电极电压控制的射极跟随器和连接到射极跟随器的有源下拉电路， 电阻器连接到输入晶体管或参考晶体管的发射极。

公开(公告)号：US5498982A

公开(公告)日：1996-03-12

申请号：US374866

申请日：1995-01-19

申请人： Venugopal Gopinathan ,  Martin J. Izzard

发明人： Venugopal Gopinathan ,  Martin J. Izzard

IPC分类号： H03K3/2885 ,  H03K19/086

CPC分类号： H03K3/2885

摘要： A method and apparatus for reducing aperture uncertainty and kick-back noise in high speed comparators is disclosed. The disclosed method is used in a comparator for comparing a first signal (INP) and a second signal (INM) and having a track mode and a regenerative mode of operation. The steps of this method are as follows. A first input current representing the first signal is switched through a first output node (OUTP) during the track mode and a second input current representing the second signal is switched through a second output node (OUTM) during the track mode. During the regenerative mode, approximately half of the first input current is switched through the first output node (OUTP) and approximately half of the first input current is switched through the second output node (OUTM). Also during the regenerative mode, approximately half of the second input current is switched through the first output node and approximately half of the second input current is switched through the second output node.

摘要翻译： 公开了一种用于降低高速比较器中的孔径不确定度和反冲噪声的方法和装置。 所公开的方法用于比较第一信号（INP）和第二信号（INM）并具有轨道模式和再生操作模式的比较器。 该方法的步骤如下。 表示第一信号的第一输入电流在轨道模式期间通过第一输出节点（OUTP）切换，并且在轨道模式期间通过第二输出节点（OUTM）切换表示第二信号的第二输入电流。 在再生模式期间，通过第一输出节点（OUTP）切换大约一半的第一输入电流，并且通过第二输出节点（OUTM）切换大约一半的第一输入电流。 而且在再生模式期间，第二输入电流的大约一半被切换通过第一输出节点，并且大约一半的第二输入电流被切换通过第二输出节点。

公开(公告)号：US5428305A

公开(公告)日：1995-06-27

申请号：US129939

申请日：1993-09-30

申请人： Puck Wong ,  Lloyd F. Linder ,  Erick M. Hirata

发明人： Puck Wong ,  Lloyd F. Linder ,  Erick M. Hirata

IPC分类号： H03K19/018 ,  H03K19/086

CPC分类号： H03K19/01837 ,  H03K19/01812

摘要： Switching between two logic circuits that produce outputs at different respective logic levels is accomplished by means of a common input differential switch that has a branch in each logic circuit. A common current source supplies current to the branches within each logic circuit. The current source remains on regardless of which logic level is selected, thereby enhancing switching speed. The logic circuits produce logic outputs at a common output differential switch, which in turn provides a selected output to a single output terminal. The logic circuits are configured so that the output from the circuit corresponding to the selected logic level dominates the output from the other logic circuit at the output differential switch.

摘要翻译： 通过在每个逻辑电路中具有分支的公共输入差分开关来实现在不同的逻辑电平处产生输出的两个逻辑电路之间的切换。 公共电流源向每个逻辑电路中的分支提供电流。 无论选择哪个逻辑电平，电流源保持不变，从而提高开关速度。 逻辑电路在公共输出差分开关产生逻辑输出，而输入差分开关又向单个输出端提供选定的输出。 逻辑电路被配置为使得来自对应于所选逻辑电平的电路的输出主导来自输出差分开关处的另一个逻辑电路的输出。

公开(公告)号：US5420524A

公开(公告)日：1995-05-30

申请号：US157242

申请日：1993-11-26

申请人： Stephen Webster

发明人： Stephen Webster

IPC分类号： H01L27/06 ,  H01L21/8222 ,  H03F1/08 ,  H03F3/45 ,  H03K19/0175 ,  H03K19/086 ,  H03K19/003

CPC分类号： H03F3/4556 ,  H03F1/083 ,  H03F3/45098 ,  H03F2203/45416 ,  H03F2203/45458 ,  H03F2203/45702

摘要： An improved differential gain stage for a bipolar monolithic integrated circuit. The integrated circuit is formed from a semiconductor substrate, and the differential gain stage includes first and second bipolar transistors. The base of the first transistor and the base of the second transistor form a differential input for the gain stage comprising non-inverting and inverting inputs respectively. The collectors of the transistors form a differential output. The differential gain stage includes a capacitor stage comprising: a peaking capacitor, and first, second, third and fourth capacitor structures. The peaking capacitor is coupled between the emitters of the first and second transistors. The first and second capacitor structures are located at a first spaced relationship from the substrate and the first capacitor is coupled to the emitter of the first transistor and the second capacitor is coupled to the emitter of the second transistor. The third and fourth capacitor structures are located at a second spaced relationship from the substrate. The third capacitor is connected to the first capacitor and the connection forms a first node. The fourth capacitor is connected to the second capacitor and the connection forms a second node. The differential gain stage also includes first and second buffers. The first buffer has an input connected to the non-inverting input of the gain stage and an output connected to the first node. The second buffer has an input connected to the inverting input of the gain stage and an output connected to the second node.

摘要翻译： 用于双极单片集成电路的改进的差分增益级。 集成电路由半导体衬底形成，差分增益级包括第一和第二双极晶体管。 第一晶体管的基极和第二晶体管的基极分别形成用于增益级的差分输入，包括非反相和反相输入。 晶体管的集电极形成差分输出。 差分增益级包括电容器级，包括：峰值电容器，以及第一，第二，第三和第四电容器结构。 峰值电容器耦合在第一和第二晶体管的发射极之间。 第一和第二电容器结构位于与衬底之间的第一间隔关系处，并且第一电容器耦合到第一晶体管的发射极，而第二电容耦合到第二晶体管的发射极。 第三和第四电容器结构位于与衬底之间的第二间隔关系。 第三电容器连接到第一电容器，并且连接形成第一节点。 第四电容器连接到第二电容器，并且连接形成第二节点。 差分增益级还包括第一和第二缓冲器。 第一缓冲器具有连接到增益级的同相输入的输入端和连接到第一节点的输出。 第二缓冲器具有连接到增益级的反相输入的输入端和连接到第二节点的输出。

公开(公告)号：US5406133A

公开(公告)日：1995-04-11

申请号：US274817

申请日：1994-07-14

申请人： Madhukar B. Vora ,  Burnell G. West

发明人： Madhukar B. Vora ,  Burnell G. West

IPC分类号： H01L21/8249 ,  H01L27/06 ,  H03K17/00 ,  H03K17/62 ,  H03K19/086 ,  H03K19/173 ,  H03K3/01 ,  H03K17/60

CPC分类号： H03K17/6285 ,  H03K17/6257 ,  H03K19/1737

摘要： A high speed switching technology suitable for implementing field programmable gate arrays using current mode logic in the high speed data path, and CMOS steering logic outside the high speed data path to enable the high speed switching logic and to implement multiplexer, selector and crossbar switch functions. High speed emitter follower logic compatible with the high speed switching logic for level shifting, buffering, and providing more current sink or source capacity is also disclosed.

摘要翻译： 适用于在高速数据通路中使用电流模式逻辑实现现场可编程门阵列的高速开关技术，以及高速数据通路外的CMOS转向逻辑，以实现高速开关逻辑和实现多路复用器，选择器和交叉开关功能 。 还公开了与高速开关逻辑兼容的高速射极跟随器逻辑，用于电平转换，缓冲和提供更多的电流吸收或源极容量。

公开(公告)号：US5373469A

公开(公告)日：1994-12-13

申请号：US890260

申请日：1992-05-29

申请人： Takashi Akioka ,  Noboru Akiyama ,  Yutaka Kobayashi ,  Tatsuyuki Ohta ,  Koyo Katsura

发明人： Takashi Akioka ,  Noboru Akiyama ,  Yutaka Kobayashi ,  Tatsuyuki Ohta ,  Koyo Katsura

IPC分类号： G11C11/417 ,  G09G5/36 ,  G09G5/39 ,  G09G5/393 ,  G11C7/06 ,  G11C11/407 ,  G11C11/409 ,  G11C11/414 ,  H03K19/013 ,  H03K19/0944 ,  G11C7/00 ,  H03K19/086

CPC分类号： H03K19/09448 ,  G09G5/363 ,  G09G5/393 ,  G11C7/062 ,  G11C7/065 ,  H03K19/0136 ,  G09G2360/121

摘要： A high-speed memory employing the pipeline technique is disclosed, in which the minimum operating cycle time is reduced by use of a latch circuit for a small signal using a bipolar transistor. A small-signal latch circuit operating at a signal smaller than an output signal level is inserted between an amplifier circuit for amplifying the data held in a memory cell circuit and an output buffer circuit. A switch signal is also interposed between the latch circuit and the amplifier circuit, thereby shortening the cycle time.

摘要翻译： 公开了一种采用流水线技术的高速存储器，其中通过使用双极晶体管的小信号的锁存电路来减小最小工作周期时间。 操作在小于输出信号电平的信号的小信号锁存电路被插入放大器电路，用于放大存储单元电路中保存的数据和输出缓冲电路。 开关信号也插入在锁存电路和放大器电路之间，从而缩短了周期时间。

公开(公告)号：US5309039A

公开(公告)日：1994-05-03

申请号：US953153

申请日：1992-09-29

申请人： Hamed Ghassemi ,  Perry H. Pelley, III

发明人： Hamed Ghassemi ,  Perry H. Pelley, III

IPC分类号： H03F3/45 ,  H03F3/50 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/086 ,  H03K3/01 ,  G06G7/12 ,  H03K17/60 ,  H03K19/02

CPC分类号： H03K19/00376 ,  H03K19/017527

摘要： A power supply dependent input buffer (20) having a differential amplifier (22), emitter-follower transistors (29 and 32), level shifting resistors (30 and 33), and power supply dependent current sources (31 and 34) receives an ECL input signal referenced to a positive power supply voltage and provides buffered level shifted signals referenced to ground. The current sources (31 and 34) receive a power supply dependent bias voltage that changes in relation to a change in the positive power supply voltage. In turn, the voltage drop across the resistors (30 and 33) changes with respect to the positive power supply voltage such that the buffered level shifted signals are constant with respect to ground. The power supply dependent input buffer (20) is for use at low power supply voltages (such as 3.3 volts), resulting in low power consumption and wider margins on following stages, such as a level converter.

摘要翻译： 具有差分放大器（22），射极跟随器晶体管（29和32），电平移位电阻（30和33）以及与电源相关的电流源（31和34）的电源依赖输入缓冲器（20）接收ECL 参考正电源电压的输入信号，并提供参考地的缓冲电平移位信号。 电流源（31和34）接收相对于正电源电压变化而变化的电源相关偏置电压。 反过来，电阻器（30和33）上的电压降相对于正电源电压变化，使得缓冲电平移位信号相对于地而恒定。 电源相关的输入缓冲器（20）用于低电源电压（例如3.3伏特），导致低功耗，并且在后续阶段（例如电平转换器）具有更宽的裕度。

公开(公告)号：US5278465A

公开(公告)日：1994-01-11

申请号：US788579

申请日：1991-11-06

申请人： Mitsuhiro Hamada

发明人： Mitsuhiro Hamada

IPC分类号： G11C11/413 ,  G11C8/06 ,  H03K19/00 ,  H03K19/086 ,  H03K19/173

CPC分类号： G11C8/06 ,  H03K19/0016

摘要： A semiconductor integrated circuit device includes a plurality of ECL gate groups. Each gate group includes a plurality of ECL gates each having a constant current source formed by a MOS transistor circuit. Each gate group also includes one gate voltage control circuit. When the gate voltage control circuit receives a signal indicating a selection state for the group, it applies a high potential bias voltage to the MOS transistor circuits of all the ECL gates within the gate group. On the other hand, when it receives a signal indicating a non-selection state, it applies a low potential bias voltage (GND potential) to them, thereby lowering the constant current to the minimum necessary amount. The circuit is capable of largely saving the current consumption by controlling the bias voltage for the MOS transistor circuits in two steps depending on the selection state or the non-selection state.

摘要翻译： 半导体集成电路器件包括多个ECL栅极组。 每个栅极组包括多个ECL门，每个ECL门具有由MOS晶体管电路形成的恒定电流源。 每个栅极组还包括一个栅极电压控制电路。 当栅极电压控制电路接收到表示该组的选择状态的信号时，对栅极组内的所有ECL栅极的MOS晶体管电路施加高电位偏置电压。 另一方面，当接收到指示非选择状态的信号时，它向它施加低电位偏置电压（GND电位），从而将恒定电流降至最低必需量。 该电路能够通过根据选择状态或非选择状态两步控制MOS晶体管电路的偏置电压来大大节省电流消耗。

公开(公告)号：US5274285A

公开(公告)日：1993-12-28

申请号：US940252

申请日：1992-09-01

申请人： David W. Boerstler ,  Edward B. Eichelberger ,  Gary T. Hendrickson ,  Charles B. Winn

发明人： David W. Boerstler ,  Edward B. Eichelberger ,  Gary T. Hendrickson ,  Charles B. Winn

IPC分类号： H03K3/286 ,  H03K19/092 ,  H03K19/086

CPC分类号： H03K3/286

摘要： A compensating upshift circuit providing low signal degradation and operating at high speed and at low power. Capacitor shunted diodes cross-couple the collectors and bases of two transistors. The cross-coupling eliminates signal swing degradation in the upshift circuit and controls current through the two collector resistors. Equalized collector resistor current eliminates signal swing degradation while providing an upshift circuit with short delays. The capacitor shunted diodes can be replaced by diode connected transistors configured to provide the necessary collector-base capacitance.

摘要翻译： 补偿升档电路提供低信号衰减，并以高速和低功率运行。 电容分流二极管交叉耦合两个晶体管的集电极和基极。 交叉耦合消除了升档电路中的信号摆幅恶化，并控制通过两个集电极电阻的电流。 均衡集电极电流消除了信号摆幅下降，同时提供了具有短延迟的升档电路。 电容器分流二极管可以由配置为提供必要的集电极基极电容的二极管连接的晶体管替代。