公开(公告)号：US20050128010A1

公开(公告)日：2005-06-16

申请号：US10304885

申请日：2002-11-26

申请人： Robert Renninger

发明人： Robert Renninger

IPC分类号： H03K3/354 ,  H03B5/24 ,  H03B27/00 ,  H03K3/03 ,  H03B1/00

CPC分类号： H03B27/00

摘要： The invention provides an oscillator apparatus having a plurality of stages, with each stage of the plurality of stages having an output node, and with a plurality of input transistors within each stage. The various output nodes are coupled to the transistor inputs of the various stages, such that for the nth stage of the plurality of stages, the input to a jth transistor, of the plurality of input transistors, is coupled to the (n-j)th output node, and wherein (n-j) is determined modulo N, where “N” is a total number of the plurality of stages and “j” is a transistor number of the plurality of input transistors within each stage. The various embodiments of the oscillator include oscillators with 6 or more stages and with 3 or more inputs per stage, plus any load input transistor, including 8 and 16 stage oscillators to produce a multiplicity of phases for any selected use. The fundamental oscillation mode frequency may also be tuned or varied through the addition of more stages and by varying the size of the transistors.

摘要翻译： 本发明提供一种具有多个级的振荡器装置，其中多级的每一级具有输出节点，并且在每个级内具有多个输入晶体管。 各个输出节点被耦合到各个级的晶体管输入端，使得对于多级的第n级阶段，输入到第i个/ 多个输入晶体管耦合到第（nj）输出节点，并且其中（nj）被确定为模N，其中“N”是多个级的总数，而“j “是每个级内的多个输入晶体管的晶体管数量。 振荡器的各种实施例包括具有6级或更多级的振荡器，每级具有3个或更多个输入，以及包括8和16级振荡器的任何负载输入晶体管，以产生用于任何所选用途的多个相位。 基本振荡模式频率也可以通过添加更多级并通过改变晶体管的尺寸来调节或改变。

公开(公告)号：US20050122178A1

公开(公告)日：2005-06-09

申请号：US10994514

申请日：2004-11-23

申请人： Kensuke Goto

发明人： Kensuke Goto

IPC分类号： H03K3/354 ,  H03K3/011 ,  H03K3/03 ,  H03L7/00

CPC分类号： H03K3/0315 ,  H03K3/011

摘要： The ring oscillator circuit with the current mirror type current limit circuit of this invention prevents the malfunction and the halt of the ring oscillator. The ring oscillator is configured with the serially connected CMOS inverters INV1-INV5 where the output of the last CMOS inverter INV5 is fed back to the input of the first CMOS inverter INV1. Also, the current mirror type current limit circuit for controlling the electric current going through the CMOS inverters INV1-INV5 is formed. The first supporting transistor T1 that helps the output of the CMOS inverter INV5 achieve the full-swing for reaching the power supply voltage Vdd and the second supporting transistor T2 that helps the output of the CMOS inverter INV5 achieve the full-swing for reaching the ground voltage Vss according to the output of the CMOS inverter INV3 two positions ahead of the last inverter INV5 are also formed.

摘要翻译： 具有本发明的电流镜式限流电路的环形振荡器电路防止环形振荡器的故障和停止。 环形振荡器配置有串行连接的CMOS反相器INV 1 -INV 5，其中最后的CMOS反相器INV5的输出反馈到第一CMOS反相器INV 1的输入端。另外，电流镜式电流限制电路 形成控制通过CMOS反相器INV 1 -INV 5的电流。 有助于CMOS反相器INV 5的输出的第一支持晶体管T 1实现满摆幅以达到电源电压Vdd和第二支持晶体管T 2，这有助于CMOS反相器INV5的输出实现全摆幅 为了达到接地电压Vss，根据CMOS反相器INV3的输出，也形成了在最后的反相器INV5之前的两个位置。

公开(公告)号：US20050077943A1

公开(公告)日：2005-04-14

申请号：US10958466

申请日：2004-10-06

申请人： Ayako Kakuda ,  Masamichi Fujito

发明人： Ayako Kakuda ,  Masamichi Fujito

IPC分类号： G11C16/06 ,  G11C7/06 ,  G11C16/02 ,  H03H11/26 ,  H03K3/354 ,  H03K5/00 ,  H03K5/13

CPC分类号： G11C7/222 ,  G11C7/04 ,  G11C7/06 ,  H03K5/133 ,  H03K2005/00123 ,  H03K2005/0013 ,  H03K2005/00143

摘要： A delay circuit comprises a constant current source, a delay stage in which an operation delay time of an output relative to an input is determined depending on a constant current produced by the constant current source, and a compensating circuit which compensates for a variation in delay characteristic of the delay stage due to a variation in temperature, a variation in power supply voltage and process variations in the opposite direction. When on resistance and threshold voltage characteristics of the compensating circuit and delay stage vary under the influence of the variations in temperature and power supply voltage or the like, a current (Id) changes following it but a current (Ip) changes so as to cancel it. As a result, the delay stage changes in its delay characteristic such that the influences such as the variations in temperature and power supply voltages are canceled out, and suppresses a variation in delay time. The compensating circuit controls a delay speed by such a current that a current characteristic relative to the variation in power supply voltage or the like becomes opposite to a device characteristic of each MOS transistor of the delay stage.

摘要翻译： 延迟电路包括恒流源，延迟级，其中相对于输入的输出的操作延迟时间取决于由恒流源产生的恒定电流，以及补偿电路，其补偿延迟的变化 由于温度的变化引起的延迟级的特性，电源电压的变化和相反方向上的工艺变化。 当在温度和电源电压等的变化的影响下，补偿电路和延迟级的导通电阻和阈值电压特性变化时，电流（Id）随之变化，但电流（Ip）发生变化从而取消 它。 结果，延迟阶段改变其延迟特性，使得诸如温度和电源电压的变化的影响被抵消，并且抑制延迟时间的变化。 补偿电路通过相对于电源电压等的变化的电流特性与延迟级的各MOS晶体管的器件特性相反的电流来控制延迟速度。

公开(公告)号：US06876236B2

公开(公告)日：2005-04-05

申请号：US10624904

申请日：2003-07-23

申请人： Norihisa Aman

发明人： Norihisa Aman

IPC分类号： H03K3/354 ,  H03K3/03 ,  H03K5/00 ,  H03L7/00 ,  H03B19/00

CPC分类号： H03L7/00 ,  H03K3/0315

摘要： A clock multiplier circuit which generates a multiple clock having a stable frequency from a reference clock without using analog devices. The clock multiplier circuit includes ring oscillator which oscillates at a higher frequency than that of the multiple clock; a reference clock counter for counting the sampling output of the reference clock by the output clock of the ring oscillator to obtain a count value of the half cycle of the reference clock; and a multiple clock counter which, in case the value obtained by dividing the count value of the half cycle of the obtained reference clock by the multiplication factor externally given is defined as a multiple count value, inverts the multiple clock output each time it counts the multiple count value by the output clock of the ring oscillator.

摘要翻译： 时钟倍增器电路，在不使用模拟装置的情况下，从参考时钟产生具有稳定频率的多个时钟。 时钟乘法器电路包括以比多个时钟频率高的频率振荡的环形振荡器; 基准时钟计数器，用于通过环形振荡器的输出时钟对参考时钟的采样输出进行计数，以获得参考时钟的半周期的计数值; 以及多个时钟计数器，在将所获得的参考时钟的半周期的计数值除以外部给出的乘法因子获得的值被定义为多个计数值的情况下，将每次计数多个时钟输出时反相 多个计数值由环形振荡器的输出时钟。

公开(公告)号：US20050046494A1

公开(公告)日：2005-03-03

申请号：US10925669

申请日：2004-08-25

申请人： Sang Lee ,  Hye Kim

发明人： Sang Lee ,  Hye Kim

IPC分类号： H03B5/00 ,  H03B1/00 ,  H03B5/12 ,  H03K3/354

CPC分类号： H03K3/354 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1243 ,  H03B2201/0208

摘要： Disclosed is a quadrature VCO (voltage controlled oscillator) which comprises a first delay cell including a first switching transistor and a second switching transistor, the first delay cell outputting first and second in-phase signals with different phases; and a second delay cell including a third switching transistor and a fourth switching transistor, the second delay cell outputting first and second quadrature-phase signals with different phases. The first and second quadrature-phase signals are applied to back gates of the first and second switching transistors, and the first and second in-phase signals are applied to back gates of the fourth and third switching transistors.

摘要翻译： 公开了一种正交VCO（压控振荡器），其包括具有第一开关晶体管和第二开关晶体管的第一延迟单元，所述第一延迟单元以不同相位输出第一和第二同相信号; 以及包括第三开关晶体管和第四开关晶体管的第二延迟单元，所述第二延迟单元输出具有不同相位的第一和第二正交相位信号。 第一和第二正交相位信号被施加到第一和第二开关晶体管的后栅极，第一和第二同相信号被施加到第四和第三开关晶体管的后栅极。

公开(公告)号：US06861916B2

公开(公告)日：2005-03-01

申请号：US10615819

申请日：2003-07-09

申请人： William J. Dally ,  Ramin Farjad-Rad ,  John W. Poulton ,  Thomas H. Greer, III ,  Hiok-Tiaq Ng ,  Teva J. Stone

发明人： William J. Dally ,  Ramin Farjad-Rad ,  John W. Poulton ,  Thomas H. Greer, III ,  Hiok-Tiaq Ng ,  Teva J. Stone

IPC分类号： H03K3/03 ,  H03K3/354 ,  H03L7/00 ,  H03L7/081 ,  H03L7/083 ,  H03L7/091 ,  H03L7/099 ,  H03L7/20 ,  H03L7/23 ,  H03L7/24 ,  H03B5/24

CPC分类号： H03L7/0805 ,  H03K3/0315 ,  H03K3/0322 ,  H03K3/354 ,  H03L7/07 ,  H03L7/0812 ,  H03L7/083 ,  H03L7/091 ,  H03L7/0995 ,  H03L7/0998 ,  H03L7/20 ,  H03L7/23 ,  H03L7/24

摘要： An oscillating signal in an oscillator is caused to phase shift toward the phase of an input signal coupled to the oscillating signal. The resonant frequency of the oscillator is about equal to an integer multiple of the frequency of the input signal. The input signal may be generated in a pulse generator to have an input pulse duration less than or equal to that of the oscillating signal. The oscillator circuit may be used as a filter to filter pulse width variations or to filter jitter from a reference clock. The oscillator circuit may also serve as a buffer by amplifying the input signal. Phase interpolation can be obtained by coupling at least one input signal with at least one oscillating signal.

摘要翻译： 引起振荡器中的振荡信号朝耦合到振荡信号的输入信号的相位移相。 振荡器的谐振频率约等于输入信号频率的整数倍。 可以在脉冲发生器中产生输入信号以具有小于或等于振荡信号的输入脉冲持续时间的输入脉冲持续时间。 振荡器电路可以用作滤波器以滤除脉冲宽度变化或者从参考时钟滤波抖动。 振荡器电路也可以通过放大输入信号作为缓冲器。 可以通过将至少一个输入信号与至少一个振荡信号耦合来获得相位插值。

公开(公告)号：US20050007201A1

公开(公告)日：2005-01-13

申请号：US10859622

申请日：2004-06-03

申请人： Byeong-hoon Lee ,  Sun-kwon Kim

发明人： Byeong-hoon Lee ,  Sun-kwon Kim

IPC分类号： H03K3/354 ,  G06F1/08 ,  G11C16/30 ,  H03K3/0231 ,  H03L7/00

CPC分类号： H03K3/0231 ,  G06F1/08 ,  G11C16/30

摘要： An oscillator includes a comparison voltage generating circuit, a comparing circuit and a clock switching circuit. The comparison voltage generating circuit is driven by a power source voltage, and generates comparison voltages that change in response to clock signals which have a frequency that varies in inverse proportion to the power source voltage and a first reference voltage. The comparing circuit compares levels of the comparison voltages to a second reference voltage and outputs logic signals having logic levels as a result of the comparison. The clock switching circuit outputs the clock signals which have a frequency that varies in inverse proportion to the power source voltage, in response to the logic signals.

摘要翻译： 振荡器包括比较电压产生电路，比较电路和时钟切换电路。 比较电压产生电路由电源电压驱动，并产生响应于具有与电源电压和第一参考电压成反比变化的频率的时钟信号而变化的比较电压。 比较电路将比较电压的电平与第二参考电压进行比较，并输出具有作为比较结果的逻辑电平的逻辑信号。 时钟切换电路响应于逻辑信号输出具有与电源电压成反比变化的频率的时钟信号。

公开(公告)号：US6163226A

公开(公告)日：2000-12-19

申请号：US318481

申请日：1999-05-25

申请人： Jules Joseph Jelinek ,  Michael Arthur Brown ,  Ramin Shirani

发明人： Jules Joseph Jelinek ,  Michael Arthur Brown ,  Ramin Shirani

IPC分类号： G05F1/56 ,  H03K3/013 ,  H03K3/03 ,  H03K3/354 ,  H03L1/00 ,  H03L7/099 ,  H03B5/02

CPC分类号： H03K3/0315 ,  G05F1/561 ,  H03K3/013 ,  H03K3/354 ,  H03L1/00 ,  H03L7/0995

摘要： A current-controlled oscillator (ICO) circuit including an all p-channel transistor based ring oscillator, a first current mirroring stage, and a second current mirroring stage. The all p-channel transistor based ring oscillator, p-channel transistors in the input structure of each amplification stage, and metal lines in the ring and from the ring to the amplification stages over an n-well improve noise immunity and tolerance. The first current mirroring stage utilizes an input current to generate a first voltage controlling a series of differential delay cells connected in a ring topology that forms the ring oscillator. The second mirroring stage utilizes a precision current to generate a second voltage controlling at least one amplification stage, which converts corresponding delay cell output signals to a single-ended logic level signal compatible with external circuitry needs. Each amplification stages utilizes the second control voltage to create a similar or ratioed copy of the precision current flowing in each amplification stage. A second embodiment of the ICO is also included, which operates at a lower frequency, thus higher bandwidth, than that of the first embodiment.

摘要翻译： 一种电流控制振荡器（ICO）电路，包括全部为p沟道晶体管的环形振荡器，第一电流镜像级和第二电流镜级。 所有基于p沟道晶体管的环形振荡器，每个放大级的输入结构中的p沟道晶体管，以及环中的金属线以及从n型阱到放大级的金属线提高了抗噪声和公差。 第一电流镜级利用输入电流来产生第一电压，该第一电压控制在形成环形振荡器的环形拓扑中连接的一系列差分延迟单元。 第二镜像级利用精密电流产生控制至少一个放大级的第二电压，其将相应的延迟单元输出信号转换成与外部电路需要兼容的单端逻辑电平信号。 每个放大级利用第二控制电压来产生在每个放大级中流动的精密电流的相似或比例的拷贝。 还包括ICO的第二实施例，其比第一实施例的频率更低的频率操作，因此具有更高的带宽。

公开(公告)号：US6163224A

公开(公告)日：2000-12-19

申请号：US378707

申请日：1999-08-23

申请人： Yoshihiro Araki ,  Michimasa Yamaguchi

发明人： Yoshihiro Araki ,  Michimasa Yamaguchi

IPC分类号： H03K3/354 ,  H03K3/0231 ,  H03K3/03 ,  H03L3/00 ,  H03L7/083 ,  H03L7/099 ,  H03L7/10 ,  H03B5/06 ,  H03L7/06

CPC分类号： H03K3/0231 ,  H03K3/03 ,  H03K3/0322 ,  H03L3/00 ,  H03L7/0995

摘要： A PLL circuit detects oscillation halt of a voltage control oscillator, generates an oscillation control signal for automatically oscillating the voltage control oscillator based upon the detected signal, and automatically restores the voltage control oscillator to a normal oscillation state by the use of the generated signal. The voltage control oscillator is structured by a ring oscillator in which a plurality of differential amplifiers are connected in a ring form. A plurality of oscillation control means are arranged for the respective inputs of the differential amplifiers so as to set the ring oscillator into an oscillationable state when the voltage control oscillator halts. The oscillation control means is controlled by the oscillating control signal.

摘要翻译： PLL电路检测电压控制振荡器的振荡停止，产生用于根据检测信号自动振荡压控振荡器的振荡控制信号，并通过使用产生的信号自动将压控振荡器恢复到正常振荡状态。 压控振荡器由环形振荡器构成，其中多个差分放大器以环形形式连接。 为差分放大器的各个输入设置多个振荡控制装置，以便当电压控制振荡器停止时将环形振荡器设置为可振荡状态。 振荡控制装置由振荡控制信号控制。

公开(公告)号：US6137370A

公开(公告)日：2000-10-24

申请号：US234981

申请日：1999-01-22

申请人： Takeshi Yamamoto

发明人： Takeshi Yamamoto

IPC分类号： H03K3/354 ,  H03B1/00 ,  H03B5/00 ,  H03B5/24 ,  H03K3/0231 ,  H03B5/02

CPC分类号： H03B5/24 ,  H03B2201/02

摘要： An oscillator having a feedback loop circuit formed by two transductors and one amplifier, and two capacitors respectively connected to the outputs of these transconductors. The transconductors and the amplifier are constructed by common-source configuration transistors to which common bias current is supplied. Since they have invert characteristics for the input voltage, the feedback loop is also self-biased by means of negative feedback operation. The oscillation signal is outputted from an arbitrary position on the feedback loop of the oscillator. According to the oscillator as constituted, the oscillation frequency can be controlled in a wide range by varying the bias current to the common-source transistors.

摘要翻译： 具有由两个转换器和一个放大器形成的反馈回路电路的振荡器和分别连接到这些跨导器的输出的两个电容器。 跨导体和放大器由共源偏置电流供给的共源晶体管构成。 由于它们对输入电压具有反转特性，所以反馈回路也通过负反馈操作自偏置。 振荡信号从振荡器的反馈回路上的任意位置输出。 根据构成的振荡器，通过改变到共源极晶体管的偏置电流，可以在宽范围内控制振荡频率。