公开(公告)号：US20160261401A1

公开(公告)日：2016-09-08

申请号：US14997056

申请日：2016-01-15

申请人： Intel IP Corporation

发明人： Hasnain Lakdawala ,  Ashoke Ravi ,  Ofir Degani ,  Bernd-Ulrich Klepser ,  Zdravko Boos ,  Georgios Palaskas ,  Stefano Pellerano ,  Paolo Madoglio

IPC分类号： H04L7/033 ,  H03L7/16 ,  H04L27/20 ,  H04B7/04 ,  H04L27/152

CPC分类号： H04L7/033 ,  H03K2005/00234 ,  H03L7/16 ,  H04B7/0413 ,  H04B7/06 ,  H04L27/152 ,  H04L27/1525 ,  H04L27/20 ,  H04W88/06

摘要： This application discusses, among other things, apparatus and methods for sharing a local oscillator between multiple wireless devices. In certain examples, an apparatus can include a central frequency synthesizer configured to provide a central oscillator signal having a first frequency, a first transmitter, the first transmitter including a first transmit digital-to-time converter (DTC) configured to receive the central oscillator signal and to provide a first transmitter signal having a second frequency, and a first receiver, the first receiver including a first receive DTC configured to receive the central oscillator signal and to provide a first receiver signal having a first receive frequency.

公开(公告)号：US20150222464A1

公开(公告)日：2015-08-06

申请号：US14612616

申请日：2015-02-03

申请人： STICHTING IMEC NEDERLAND

发明人： Yao-Hong Liu ,  Wilhelmus Matthias Clemens Dolmans ,  Johannes Henricus Cornelus van den Heuvel

IPC分类号： H04L27/22 ,  H04L27/148 ,  H04L27/152

CPC分类号： H04L27/22 ,  H03J1/005 ,  H04B1/0028 ,  H04B1/30 ,  H04L27/148 ,  H04L27/152

摘要： The present disclosure relates to a front-end system for a radio device. In one example, a front-end system comprises a converter, the converter comprising a mixer configured for down-converting a radio frequency signal into a baseband signal by using a local oscillator signal generated by a signal generator, and characterized in that, the converter further comprises a quantizer arranged for quantizing the baseband signal into a digital signal. Further, the signal generator may be configured for generating, based on the digital signal, the local oscillator signal such that it is synchronized with the radio frequency signal.

摘要翻译： 本公开涉及无线电设备的前端系统。 在一个示例中，前端系统包括转换器，转换器包括配置为通过使用由信号发生器产生的本地振荡器信号将射频信号下变频为基带信号的混频器，其特征在于，转换器 还包括量化器，被配置为将基带信号量化为数字信号。 此外，信号发生器可以被配置为基于数字信号产生本地振荡器信号，使得其与射频信号同步。

公开(公告)号：US06912380B2

公开(公告)日：2005-06-28

申请号：US09819810

申请日：2001-03-29

申请人： Taizo Yamawaki ,  Satoshi Tanaka ,  Norio Hayashi ,  Kazuo Watanabe ,  Robert Astle Henshaw

发明人： Taizo Yamawaki ,  Satoshi Tanaka ,  Norio Hayashi ,  Kazuo Watanabe ,  Robert Astle Henshaw

IPC分类号： H03L7/093 ,  H03L7/07 ,  H03L7/08 ,  H03L7/085 ,  H03L7/10 ,  H04B1/40 ,  H04L27/152 ,  H04B1/06

CPC分类号： H03L7/085 ,  H03L7/07 ,  H03L7/10 ,  H03L2207/12

摘要： In a PLL circuit, and a wireless mobile station with that PLL circuit, an LPF charging constant current source, a discharging constant current source and a high-speed charging constant current source are connected to an output terminal of a phase comparator with current mode output. When a convergence frequency of the PLL circuit is low, an input voltage of a VCO is increased from OV so as to be converged by using the constant current source. However, when the convergence frequency of the PLL circuit is high, the input voltage of the PLL circuit is temporarily increased to the maximum voltage by using the constant current source. Thereafter, the input voltage is gradually dropped from the maximum voltage so as to be converged by using the constant current source.

摘要翻译： 在PLL电路和具有该PLL电路的无线移动站中，LPF充电恒流源，放电恒流源和高速充电恒流源连接到具有电流模式输出的相位比较器的输出端 。 当PLL电路的收敛频率低时，VCO的输入电压从0V增加，以便通过使用恒流源而被收敛。 然而，当PLL电路的收敛频率高时，通过使用恒流源将PLL电路的输入电压临时增加到最大电压。 此后，输入电压从最大电压逐渐降低，以便通过使用恒流源来收敛。

公开(公告)号：US06904538B2

公开(公告)日：2005-06-07

申请号：US09989272

申请日：2001-11-20

申请人： Jack P. Glas ,  Vladimir I. Prodanov

发明人： Jack P. Glas ,  Vladimir I. Prodanov

IPC分类号： H04L12/28 ,  H04L12/56 ,  H04L27/152 ,  H04B1/04

CPC分类号： H04L27/1525 ,  H04W84/12 ,  H04W84/18

摘要： The present invention is directed towards a data detector for deriving a data signal from an incoming radio frequency input. The data detector comprises a delay logic which receives an unfiltered signal in quadrature and in-phase components, and applies a delay to each of the in-phase and quadrature phase components of the unfiltered input signal. The detector further comprises a first multiplication logic that multiplies the delayed in-phase component of the unfiltered signal by the quadrature phase component of the unfiltered signal to obtain a first result, and a second multiplication logic that multiplies the delayed quadrature phase component of the unfiltered signal by the in-phase component of the unfiltered signal to obtain a second result. Finally, an adder adds the first result with the second result to generate a data signal. In alternative embodiments a post detection correction algorithm may be added to improve performance.

摘要翻译： 本发明涉及一种用于从输入射频输入导出数据信号的数据检测器。 数据检测器包括延迟逻辑，该延迟逻辑以正交和同相分量接收未滤波的信号，并对未滤波的输入信号的每个同相和正交相位分量施加延迟。 检测器还包括第一乘法逻辑，其将未滤波信号的延迟同相分量乘以未滤波信号的正交相位分量以获得第一结果;以及第二乘法逻辑，其将未滤波的延迟正交相位分量 信号由未滤波信号的同相分量获得第二结果。 最后，加法器将第一结果与第二结果相加以产生数据信号。 在替代实施例中，可以添加后检测校正算法以改善性能。

公开(公告)号：US6085073A

公开(公告)日：2000-07-04

申请号：US33047

申请日：1998-03-02

申请人： Keith Charles Palermo ,  Kurt Albert Kallman

发明人： Keith Charles Palermo ,  Kurt Albert Kallman

IPC分类号： H04L27/152 ,  H04B1/16

CPC分类号： H04L27/1525

摘要： A method and system for reducing the sampling rate of a signal for use with high modulation index frequency modulated signals reduces the power consumption and processing requirements of the digital signal processing equipment which performs the demodulation. In a preferred embodiment, a high modulation index FM signal is divided into in-phase and quadrature phase components by a downconverter (FIG. 1, 10). These components are sampled by analog to digital converters (20, 21) and input to a delay element (40, 41). The resulting delayed and undelayed samples are conveyed to downsamplers (60-63) where the sampling rate is reduced. The undelayed in-phase and delayed quadrature phase components are multiplied together by a first multiplier (70) while the undelayed quadrature phase and delayed in-phase components are multiplied together by a second multiplier (71). The output of the second multiplier (71) is then subtracted from the output of the first multiplier (70) by a subtractor (80) which outputs baseband audio or data.

摘要翻译： 用于降低高调制频率调制信号使用的信号的采样率的方法和系统降低了进行解调的数字信号处理设备的功耗和处理要求。 在优选实施例中，高调制度调频信号通过下变频器被分成同相和正交相分量（图1,10）。 这些组件由模数转换器（20,21）采样并输入到延迟元件（40,41）。 所得到的延迟和未延迟的样品被传送到采样速率降低的下采样器（60-63）。 不延时的同相和延迟正交相位分量由第一乘法器（70）相乘，而不延时正交相位和延迟的同相分量由第二乘法器（71）相乘。 然后，通过输出基带音频或数据的减法器（80）从第一乘法器（70）的输出中减去第二乘法器（71）的输出。

公开(公告)号：US5912930A

公开(公告)日：1999-06-15

申请号：US825764

申请日：1997-04-01

申请人： Motoya Iwasaki

发明人： Motoya Iwasaki

IPC分类号： H04L27/22 ,  H04L27/227 ,  H03D3/00 ,  H03D3/22 ,  H04L27/152

CPC分类号： H04L25/03885 ,  H04L27/2276

摘要： The invention provides a PSK signal demodulation device of small circuit scale that is capable of both rapid synchronization pull-in and stable demodulation operation following demodulation synchronization pull-in. To achieve these capabilities, the phase shift keying signal demodulation device of this invention is provided with an adaptive line enhancer demodulation circuit, a PLL demodulation circuit, and a switching circuit that switches the demodulation circuits from the adaptive line enhancer demodulation circuit to the PLL demodulation circuit. The switching circuit switches between the demodulation circuits such that, upon start of input of an N-phase PSK signal, demodulation is effected by the adaptive line enhancer demodulation circuit until phase synchronization is established between the input N-phase PSK signal and the recovered carrier, and demodulation is effected by the PLL demodulation circuit after establishment of phase synchronization.

摘要翻译： 本发明提供一种小型电路规模的PSK信号解调装置，其能够在解调同步拉入之后进行快速同步拉入和稳定的解调操作。 为了实现这些能力，本发明的相移键控信号解调装置设置有自适应线路增强器解调电路，PLL解调电路和切换电路，其将解调电路从自适应线路增强器解调电路切换到PLL解调 电路。 开关电路在解调电路之间切换，使得在开始输入N相PSK信号时，解调由自适应线路增强器解调电路实现，直到在输入的N相PSK信号和恢复的载波之间建立相位同步 并且在相位同步建立之后由PLL解调电路进行解调。

公开(公告)号：US5581579A

公开(公告)日：1996-12-03

申请号：US523032

申请日：1995-09-01

申请人： Nan-Sheng Lin ,  Ravi Subramanian ,  Kenkichi Suzuki

发明人： Nan-Sheng Lin ,  Ravi Subramanian ,  Kenkichi Suzuki

IPC分类号： H04L7/033 ,  H04L7/04 ,  H04L27/152 ,  H04L27/22

CPC分类号： H04L27/152 ,  H04L7/0334 ,  H04L7/042

摘要： In a digital wireless communication system operating between a first unit and a second unit, the first unit transmits a digitally encoded RF signal at a first frequency in a plurality of a non-contiguous time slots to the second unit. The second unit receives the digitally encoded RF signals. The received RF digitally encoded signal is converted to an intermediate frequency (IF). An A to D converter samples the received IF digitally encoded signals and generates a plurality of discrete binary symbols during one of the plurality of non-contiguous time slots. A phase error signal is generated for each one of the plurality of discrete binary symbols. A frequency error signal is generated for the subsequent symbol in accordance with .DELTA.f(n+1)=.DELTA.f(n)+g.sub.1 (.crclbar.(n)-.crclbar.(n)). The conversion of the RF signal to intermediate frequency is controlled in response to the frequency error signal. The control is adjusted after the one time slot but prior to the commencement of a subsequent one of the plurality of non-contiguous time slots.

摘要翻译： 在第一单元和第二单元之间操作的数字无线通信系统中，第一单元以多个非连续时隙中的第一频率向第二单元发送数字编码的RF信号。 第二单元接收数字编码的RF信号。 所接收的RF数字编码信号被转换成中频（IF）。 A至D转换器对所接收的IF数字编码信号进行采样，并在多个非连续时隙之一产生多个离散二进制符号。 对于多个离散二进制符号中的每一个生成相位误差信号。 根据DELTA f（n + 1）= DELTA f（n）+ g1（（ - ）（n） - + E，otl（ - ）+ EE（n））为后续符号生成频率误差信号。 响应于频率误差信号来控制RF信号到中频的转换。 控制在一个时隙之后但是在多个非连续时隙中的后续的一个时间段的开始之前被调整。

公开(公告)号：US5471187A

公开(公告)日：1995-11-28

申请号：US309265

申请日：1994-09-20

申请人： Jens Hansen ,  Benny Madsen ,  Jens T. Petersen

发明人： Jens Hansen ,  Benny Madsen ,  Jens T. Petersen

IPC分类号： H03L7/18 ,  H03B1/00 ,  H03B5/18 ,  H03C3/09 ,  H03L7/183 ,  H04B1/26 ,  H04B1/40 ,  H04B1/56 ,  H04L5/14 ,  H04L27/10 ,  H04L27/12 ,  H04L27/148 ,  H04L27/152 ,  H03K9/08 ,  H03K3/017

CPC分类号： H03C3/095 ,  H03B5/18 ,  H03L7/183 ,  H04B1/408 ,  H04L27/10 ,  H04L27/12 ,  H04L27/148 ,  H04L27/152 ,  H04L5/143 ,  H04L5/1492 ,  H03B2201/0208 ,  H03L2207/06 ,  H04B1/56

摘要： A radio frequency (RF) transceiver includes a direct modulation transmitter and single down-conversion receiver for operation in a time-division-duplex (TDD) telecommunications environment. A single RF signal source, in the form of a phase-lock-loop (PLL), is used on a time-shared basis to provide both the carrier signal for the transmitter and the local oscillator (LO) signal for the receiver. In the transmitter, direct modulation is effected by modulating a voltage-controlled oscillator (VCO) in the PLL with a burst of the transmit data while opening the loop and holding the loop feedback tuning voltage constant. In the receiver, a self-adjusting comparator threshold is provided for automatically setting and adjusting a demodulated signal comparison threshold used in retrieving the data and data clock from the demodulated receive signal. The interface between the transmitter and receiver and the host controller provides the control signals needed for the time-sharing of the single RF signal source, the proper programming of the PLL for the different transmitter carrier and receiver LO frequencies, the PLL loop control for the direct modulation of the VCO, and the enablement, or powering down, of the transmitter and receiver sections to minimize transceiver power consumption.

摘要翻译： 射频（RF）收发器包括用于在时分双工（TDD）电信环境中操作的直接调制发射机和单个下变频接收机。 在时间共享的基础上使用单相RF锁相环（PLL）形式的RF信号源，为接收机提供发射机的载波信号和本地振荡器（LO）信号。 在发射机中，通过在打开环路并保持环路反馈调谐电压恒定的情况下，通过发射数据的突发调制PLL中的压控振荡器（VCO）来实现直接调制。 在接收机中，提供自调整比较器阈值，用于自动设置和调整用于从解调的接收信号中检索数据和数据时钟的解调信号比较阈值。 发射机和接收机与主机控制器之间的接口提供单个RF信号源的时间分配所需的控制信号，针对不同发射机载波和接收机LO频率的PLL的适当编程，PLL环路控制 VCO的直接调制，以及发射机和接收机部分的启用或掉电，以最小化收发器功率消耗。

公开(公告)号：US5451899A

公开(公告)日：1995-09-19

申请号：US302510

申请日：1994-09-08

申请人： Rodney J. Lawton

发明人： Rodney J. Lawton

IPC分类号： H04B1/30 ,  H03D3/00 ,  H03D3/24 ,  H04L27/152 ,  H04L27/148

CPC分类号： H03D3/007 ,  H03D3/24 ,  H04L27/1525

摘要： In a direct conversion receiver in which received radio frequency signals are mixed with quadrature local oscillator signals in I and Q channels, the output signals from the mixers are applied to a phase detector by way of respective frequency tracking filters to reduce the noise bandwidth and improve the sensitivity.

摘要翻译： 在接收到的射频信号与I和Q通道中的正交本地振荡器信号混合的直接转换接收机中，来自混频器的输出信号通过相应的频率跟踪滤波器被施加到相位检测器，以降低噪声带宽并改善 灵敏度。

公开(公告)号：US5408695A

公开(公告)日：1995-04-18

申请号：US999308

申请日：1992-12-31

申请人： Barry L. Dorr

发明人： Barry L. Dorr

IPC分类号： H04B17/00 ,  H04L27/152 ,  H04L27/08

CPC分类号： H04L27/152 ,  H04B17/104 ,  H04B17/18

摘要： An apparatus automatically determines the frequency deviation of a transmitter by analyzing a signal received from the transmitter. The apparatus automatically corrects the incoming signal for the improper deviation and maintains a record of the frequency deviation errors. Transmitters which consistently exhibit errors may then be recalled for servicing. This device increases data transmission reliability, improves compliance with FCC licensing regulations and reduces maintenance costs.

摘要翻译： 设备通过分析从发射机接收的信号来自动确定发射机的频率偏差。 该设备自动校正输入信号的不正确偏差，并保持频偏偏差的记录。 始终显示错误的变送器可能被召回进行维修。 该设备提高了数据传输的可靠性，提高了FCC许可规定的符合性，并降低了维护成本。