公开(公告)号：US09536803B2

公开(公告)日：2017-01-03

申请号：US14847558

申请日：2015-09-08

申请人： RF Micro Devices, Inc.

发明人： David Charles Sheridan ,  Robert Charles Dry ,  Don Willis

IPC分类号： H01L23/34 ,  H01L25/07 ,  H05K7/20 ,  H01L27/095 ,  H01L27/088 ,  H01L29/10 ,  H01L23/373 ,  H01L23/367 ,  H01L23/498 ,  H01L29/423

CPC分类号： H01L23/345 ,  H01L23/3677 ,  H01L23/3736 ,  H01L23/49827 ,  H01L23/49844 ,  H01L25/072 ,  H01L27/088 ,  H01L27/095 ,  H01L29/1079 ,  H01L29/4232 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/48227 ,  H01L2224/73265 ,  H05K7/205 ,  H05K7/20963 ,  H01L2924/00014 ,  H01L2924/00

摘要： An integrated power module having a depletion mode device and an enhancement mode device that is configured to prevent an accidental on-state condition for the depletion mode device during a gate signal loss is disclosed. In particular, the disclosed integrated power module is structured to provide improved isolation and thermal conductivity. The structure includes a substrate having a bottom drain pad for the depletion mode device disposed on the substrate and an enhancement mode device footprint-sized cavity that extends through the substrate to the bottom drain pad. A thermally conductive and electrically insulating slug substantially fills the cavity to provide a higher efficient thermal path between the enhancement mode device and the bottom drain pad for the depletion mode device.

摘要翻译： 具有耗尽型器件和增强型器件的集成电源模块被配置为在栅极信号丢失期间防止耗尽型器件的意外导通状态。 特别地，所公开的集成功率模块被构造成提供改进的隔离和导热性。 该结构包括具有用于耗尽型器件的底部漏极焊盘的衬底，其设置在衬底上，以及增强模式器件占位面积尺寸的空腔，其延伸穿过衬底到底部漏极焊盘。 导热和电绝缘的芯块基本上填充空腔，以在增强模式器件和用于耗尽型器件的底部漏极焊盘之间提供更高效的热路径。

公开(公告)号：US09431529B2

公开(公告)日：2016-08-30

申请号：US14625376

申请日：2015-02-18

申请人： Samsung Electronics Co., Ltd.

发明人： Ryan M. Hatcher ,  Jorge A. Kittl ,  Robert C. Bowen

IPC分类号： H01L29/745 ,  H01L29/74 ,  H01L29/768 ,  H01L27/095 ,  H01L21/335 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06

CPC分类号： H01L29/78 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/36 ,  H01L29/66439 ,  H01L29/66477 ,  H01L29/775

摘要： Exemplary embodiments are disclosed for a semi-metal transistor, comprising: a semi-metal contact region adjacent to a metal contact; at least one semiconductor terminal; and a semi-metal transition region connected between the contact region and the semiconductor terminal that transitions from a substantially zero gap semi-metal beginning at an interface of the contact region into a semiconductor with an energy band gap towards the semiconductor terminal.

摘要翻译： 公开了用于半金属晶体管的示例性实施例，包括：与金属接触相邻的半金属接触区域; 至少一个半导体端子; 以及连接在所述接触区域和所述半导体端子之间的半金属过渡区域，所述半金属过渡区域从从所述接触区域的界面开始的半金属基本上为零的间隙向具有朝向所述半导体端子的能带隙的半导体转变。

公开(公告)号：US09318487B2

公开(公告)日：2016-04-19

申请号：US13937542

申请日：2013-07-09

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jun-De Jin ,  Tzu-Jin Yeh ,  Chewn-Pu Jou

IPC分类号： H01L27/088 ,  H03F1/22 ,  H01L21/8238 ,  H01L27/095 ,  H03F3/213 ,  H01L27/092

CPC分类号： H01L27/0883 ,  H01L21/8236 ,  H01L21/8238 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823885 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/095 ,  H01L29/0649 ,  H01L29/66666 ,  H01L29/66848 ,  H01L29/7827 ,  H01L29/812 ,  H03F1/223 ,  H03F3/213

摘要： A power cell designed for an RF power amplifier comprises an enhancement MOSFET formed in an P-Well in an P-Substrate and a depletion or Schottky MOSFET formed in an N-Well in the same P-Substrate with a horizontal or a vertical channel between the source, drain, and gate electrodes of the depletion or Schottky MOSFET. The source node of the enhancement MOSFET and source node of the depletion or Schottky MOSFET are connected together to form the power cell.

摘要翻译： 为RF功率放大器设计的功率单元包括形成在P基板中的P阱中的增强型MOSFET和形成在相同P-基板中的N阱中的耗尽或肖特基MOSFET，其中水平或垂直通道介于 耗尽或肖特基MOSFET的源极，漏极和栅电极。 增强MOSFET的源节点和耗尽型或肖特基MOSFET的源极节点连接在一起形成功率单元。

公开(公告)号：US09165922B2

公开(公告)日：2015-10-20

申请号：US14015986

申请日：2013-08-30

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Akira Yoshioka ,  Yasunobu Saito ,  Hidetoshi Fujimoto ,  Takeshi Uchihara ,  Naoko Yanase ,  Toshiyuki Naka ,  Tetsuya Ohno ,  Tasuku Ono

IPC分类号： H01L27/06 ,  H01L27/095

CPC分类号： H01L27/0629 ,  H01L27/095 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/73265 ,  H01L2924/12032 ,  H01L2924/00 ,  H01L2924/00014

摘要： According to an embodiment, a semiconductor device includes a conductive substrate, a Schottky barrier diode, and a field-effect transistor. The Schottky barrier diode is mounted on the conductive substrate and includes an anode electrode and a cathode electrode. The anode electrode is electrically connected to the conductive substrate. The field-effect transistor is mounted on the conductive substrate and includes a source electrode, a drain electrode, and a gate electrode. The source electrode of the field-effect transistor is electrically connected to the cathode electrode of the Schottky barrier diode. The gate electrode of the field-effect transistor is electrically connected to the anode electrode of the Schottky barrier diode.

摘要翻译： 根据实施例，半导体器件包括导电衬底，肖特基势垒二极管和场效应晶体管。 肖特基势垒二极管安装在导电基板上，并包括阳极电极和阴极电极。 阳极电极与导电性基板电连接。 场效应晶体管安装在导电基板上，包括源电极，漏电极和栅电极。 场效应晶体管的源电极电连接到肖特基势垒二极管的阴极。 场效晶体管的栅电极与肖特基势垒二极管的阳极电连接。

公开(公告)号：US09142631B2

公开(公告)日：2015-09-22

申请号：US12725812

申请日：2010-03-17

申请人： Van Mieczkowski ,  Helmut Hagleitner ,  Zoltan Ring

发明人： Van Mieczkowski ,  Helmut Hagleitner ,  Zoltan Ring

IPC分类号： H01L27/095 ,  H01L29/47 ,  H01L29/423 ,  H01L29/778 ,  H01L29/20

CPC分类号： H01L29/475 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/7787

摘要： Semiconductor Schottky barrier devices include a wide bandgap semiconductor layer, a Schottky barrier metal layer on the wide bandgap semiconductor layer and forming a Schottky junction, a current spreading layer on the Schottky barrier metal layer remote from the wide bandgap semiconductor layer and two or more diffusion barrier layers between the current spreading layer and the Schottky barrier metal layer. The first diffusion barrier layer reduces mixing of the current spreading layer and the second diffusion barrier layer at temperatures of the Schottky junction above about 300° C. and the second diffusion barrier layer reduces mixing of the first diffusion barrier layer and the Schottky barrier metal layer at the temperatures of the Schottky junction above about 300° C.

摘要翻译： 半导体肖特基势垒器件包括宽带隙半导体层，宽带隙半导体层上的肖特基势垒金属层和形成肖特基结，在远离宽带隙半导体层的肖特基势垒金属层上的电流扩散层和两个或更多个扩散 电流扩散层和肖特基势垒金属层之间的阻挡层。 第一扩散阻挡层在约300℃以上的肖特基结温度下降低了电流扩散层和第二扩散阻挡层的混合，第二扩散阻挡层减少了第一扩散阻挡层和肖特基势垒金属层的混合 在高于约300℃的肖特基结的温度下

公开(公告)号：US09130063B2

公开(公告)日：2015-09-08

申请号：US14496617

申请日：2014-09-25

申请人： Sanken Electric Co., LTD.

发明人： Hiroko Kawaguchi ,  Hiromichi Kumakura ,  Satoru Washiya ,  Toru Yoshie

IPC分类号： H01L27/095 ,  H01L29/47 ,  H01L29/812 ,  H01L31/07 ,  H01L31/108 ,  H01L29/872 ,  H01L29/45 ,  H01L21/283 ,  H01L29/16

CPC分类号： H01L29/872 ,  H01L21/0485 ,  H01L21/0495 ,  H01L21/283 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/47

摘要： A semiconductor device having a main electrode connected to a first semiconductor region and a second semiconductor layer on a semiconductor substrate so that a pn-junction diode is formed with the first semiconductor region being interposed and a Schottky barrier diode is formed with the second semiconductor layer being interposed on a surface of the semiconductor substrate, the semiconductor device includes a first electrode configured to ohmic-contact the first semiconductor region; a second electrode configured to Schottky-contact the second semiconductor layer and not having a portion directly contacting the first electrode; and a conductive reaction suppression layer to suppress a reaction between a material configuring the first electrode and a material configuring the second electrode are provided on the surface of the semiconductor substrate, and the main electrode is electrically connected to the first electrode and the second electrode.

摘要翻译： 一种半导体器件，其具有连接到第一半导体区域的主电极和在半导体衬底上的第二半导体层，使得形成有第一半导体区域的pn结二极管并且形成肖特基势垒二极管，其中第二半导体层 被插入在所述半导体衬底的表面上，所述半导体器件包括构造为与所述第一半导体区域欧姆接触的第一电极; 第二电极，其被配置为与所述第二半导体层肖特基接触，并且不具有直接接触所述第一电极的部分; 并且在半导体衬底的表面上设置用于抑制构成第一电极的材料和构成第二电极的材料之间的反应的导电反应抑制层，并且主电极与第一电极和第二电极电连接。

公开(公告)号：US20150236017A1

公开(公告)日：2015-08-20

申请号：US14184976

申请日：2014-02-20

申请人： Cree, Inc.

发明人： Fabian Radulescu

IPC分类号： H01L27/095 ,  H01L29/423 ,  H01L29/778 ,  H01L21/8232 ,  H01L29/16 ,  H01L29/205 ,  H01L29/20 ,  H01L29/66 ,  H01L29/812

CPC分类号： H01L27/095 ,  H01L21/8232 ,  H01L27/0605 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42316 ,  H01L29/4238 ,  H01L29/66068 ,  H01L29/66462 ,  H01L29/66863 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/812 ,  H01L29/8128

摘要： A first dielectric layer including a first opening is provided on a first surface of a semiconductor layer. A second dielectric layer is provided on top of the first dielectric layer in the first opening. A first portion of the second dielectric layer is then removed, such that a second portion of the second dielectric layer remains in the first opening. The first dielectric layer is then removed, leaving only the second portion of the second dielectric layer on the surface of the semiconductor layer. An epitaxial layer or a base dielectric layer is grown on the exposed portions of the first surface of the semiconductor layer not covered by the second portion of the second dielectric layer. The second portion of the second dielectric layer is then removed to define one or more contact windows, and a contact metal is deposited in the one or more contact windows.

摘要翻译： 包括第一开口的第一电介质层设置在半导体层的第一表面上。 在第一开口中的第一电介质层的顶部上设置第二电介质层。 然后去除第二介电层的第一部分，使得第二介电层的第二部分保留在第一开口中。 然后去除第一介电层，仅在半导体层的表面上留下第二介电层的第二部分。 在半导体层的未被第二电介质层的第二部分覆盖的第一表面的暴露部分上生长外延层或基底电介质层。 然后去除第二介电层的第二部分以限定一个或多个接触窗口，并且接触金属沉积在一个或多个接触窗口中。

公开(公告)号：US20150137139A1

公开(公告)日：2015-05-21

申请号：US14574982

申请日：2014-12-18

申请人： Infineon Technologies Austria AG

发明人： Franz Hirler ,  Andreas Meiser

IPC分类号： H01L27/095 ,  H01L29/201 ,  H01L29/205 ,  H01L21/265 ,  H01L27/092 ,  H01L29/04 ,  H01L29/778 ,  H01L29/20 ,  H01L29/16

CPC分类号： H01L27/095 ,  H01L21/265 ,  H01L21/76283 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/092 ,  H01L29/045 ,  H01L29/16 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/7787 ,  H01L29/78

摘要： A semiconductor device is disclosed. In one embodiment, the semiconductor device includes two different semiconductor materials. The two semiconductor materials are arranged adjacent one another in a common plane.

摘要翻译： 公开了一种半导体器件。 在一个实施例中，半导体器件包括两种不同的半导体材料。 两个半导体材料在公共平面中彼此相邻布置。

公开(公告)号：US08928410B2

公开(公告)日：2015-01-06

申请号：US13803792

申请日：2013-03-14

申请人： ACCO Semiconductor, Inc.

发明人： Alexandre G. Bracale ,  Denis A. Masliah

IPC分类号： H03F3/16 ,  H01L27/088 ,  H01L21/82 ,  H01L27/06 ,  H03F1/22 ,  H03F3/195 ,  H03F3/24 ,  H03F1/02 ,  H03F1/56 ,  H03F3/193 ,  H01L27/095 ,  H01L27/098

CPC分类号： H01L27/088 ,  H01L21/82 ,  H01L27/0617 ,  H01L27/095 ,  H01L27/098 ,  H03F1/0266 ,  H03F1/223 ,  H03F1/56 ,  H03F3/1935 ,  H03F3/195 ,  H03F3/245 ,  H03F2200/18 ,  H03F2200/222 ,  H03F2200/387

摘要： Electronic circuits and methods are provided for various applications including signal amplification. An exemplary electronic circuit comprises a MOSFET and a dual-gate JFET in a cascode configuration. The dual-gate JFET includes top and bottom gates disposed above and below the channel. The top gate of the JFET is controlled by a signal that is dependent upon the signal controlling the gate of the MOSFET. The control of the bottom gate of the JFET can be dependent or independent of the control of the top gate. The MOSFET and JFET can be implemented as separate components on the same substrate with different dimensions such as gate widths.

摘要翻译： 提供电子电路和方法用于各种应用，包括信号放大。 示例性电子电路包括MOSFET和共栅二极管配置的双栅极JFET。 双栅极JFET包括设置在通道上方和下方的顶部和底部门。 JFET的顶栅由信号控制，该信号取决于控制MOSFET栅极的信号。 JFET的底栅的控制可以取决于或不依赖于顶栅的控制。 MOSFET和JFET可以在不同尺寸（如栅极宽度）的同一衬底上实现为单独的组件。

公开(公告)号：US08878327B2

公开(公告)日：2014-11-04

申请号：US13730649

申请日：2012-12-28

申请人： Industrial Technology Research Institute

发明人： Cheng-Tyng Yen ,  Young-Shying Chen ,  Chien-Chung Hung ,  Chwan-Ying Lee

IPC分类号： H01L27/095 ,  H01L29/47 ,  H01L29/812 ,  H01L31/07 ,  H01L29/04 ,  H01L31/036 ,  H01L31/108 ,  H01L29/80 ,  H01L31/112 ,  H01L31/00 ,  H01L29/66 ,  H01L29/872

CPC分类号： H01L29/872 ,  H01L29/47 ,  H01L29/6606 ,  H01L29/8725

摘要： A Schottky barrier device includes a semiconductor substrate, a first contact metal layer, a second contact metal layer and an insulating layer. The semiconductor substrate has a first surface, and plural trenches are formed on the first surface. Each trench includes a first recess having a first depth and a second recess having a second depth. The second recess extends down from the first surface while the first recess extends down from the second recess. The first contact metal layer is formed on the second recess. The second contact metal layer is formed on the first surface between two adjacent trenches. The insulating layer is formed on the first recess. A first Schottky barrier formed between the first contact metal layer and the semiconductor substrate is larger than a second Schottky barrier formed between the second contact metal layer and the semiconductor substrate.

摘要翻译： 肖特基势垒器件包括半导体衬底，第一接触金属层，第二接触金属层和绝缘层。 半导体衬底具有第一表面，并且在第一表面上形成多个沟槽。 每个沟槽包括具有第一深度的第一凹部和具有第二深度的第二凹部。 第二凹部从第一表面向下延伸，同时第一凹部从第二凹部向下延伸。 第一接触金属层形成在第二凹部上。 第二接触金属层形成在两个相邻沟槽之间的第一表面上。 绝缘层形成在第一凹部上。 形成在第一接触金属层和半导体衬底之间的第一肖特基势垒大于形成在第二接触金属层和半导体衬底之间的第二肖特基势垒。