Write bank group mask during arbitration

    公开(公告)号:US11669274B2

    公开(公告)日:2023-06-06

    申请号:US17218676

    申请日:2021-03-31

    Abstract: A memory controller includes an arbiter for selecting memory requests from a command queue for transmission to a dynamic random access memory (DRAM) memory. The arbiter includes a bank group tracking circuit that tracks bank group numbers of three or more prior write requests selected by the arbiter. The arbiter also includes a selection circuit that selects requests to be issued from the command queue, and prevents selection of write requests and associated activate commands to the tracked bank group numbers unless no other write request is eligible in the command queue. The bank group tracking circuit indicates that a prior write request and the associated activate commands are eligible to be issued after a number of clock cycles has passed corresponding to a minimum write-to-write timing period for a bank group of the prior write request.

    THROTTLING HULL SHADERS BASED ON TESSELLATION FACTORS IN A GRAPHICS PIPELINE

    公开(公告)号:US20230169728A1

    公开(公告)日:2023-06-01

    申请号:US17974199

    申请日:2022-10-26

    Inventor: Nishank PATHAK

    CPC classification number: G06T17/20 G06T15/005

    Abstract: A processing system includes hull shader circuitry that launches thread groups including one or more primitives. The hull shader circuitry also generates tessellation factors that indicate subdivisions of the primitives. The processing system also includes throttling circuitry that estimates a primitive launch time interval for the domain shader based on the tessellation factors and selectively throttles launching of the thread groups from the hull shader circuitry based on the primitive launch time interval of the domain shader and a hull shader latency. In some cases, the throttling circuitry includes a first counter that is incremented in response to launching a thread group from the buffer and a second counter that modifies the first counter based on a measured latency of the domain shader.

    Memory calibration system and method

    公开(公告)号:US11664062B2

    公开(公告)日:2023-05-30

    申请号:US16938855

    申请日:2020-07-24

    Abstract: A method for performing stutter of dynamic random access memory (DRAM) where a system on a chip (SOC) initiates bursts of requests to the DRAM to fill buffers to allow the DRAM to self-refresh is disclosed. The method includes issuing, by a system management unit (SMU), a ForceZQCal command to the memory controller to initiate the stutter procedure in response to receiving a timeout request, such as an SMU ZQCal timeout request, periodically issuing a power platform threshold (PPT) request, by the SMU, to the memory controller, and sending a ForceZQCal command prior to a PPT request to ensure re-training occurs after ZQ Calibration. The ForceZQCal command issued prior to PPT request may reduce the latency of the stutter. The method may further include issuing a ForceZQCal command prior to each periodic re-training.

    Sense amplifier with increased headroom

    公开(公告)号:US11657856B2

    公开(公告)日:2023-05-23

    申请号:US17113346

    申请日:2020-12-07

    CPC classification number: G11C7/065 G11C15/04 G11C2207/063

    Abstract: Systems, apparatuses, and methods for implementing a sampling circuit with increased headroom are disclosed. A sampling circuit includes at least a pair of input signal transistors connected via their drains to a cross-coupled pair of state nodes. The cross-coupled pair of state nodes are coupled to a tail transistor device via the sources of N-type transistors. When clock goes low, the circuit precharges the cross-coupled pair of state nodes while simultaneously attempting to amplify the difference between the pair of input signals. The amplification is performed by a pair of transistors in series between a source of each input signal transistor and ground. Each gate of the pair of transistors is connected to an inverted clock signal. When clock goes high, the circuit stops precharging and a voltage difference between the pair of input signals is regenerated to create a resulting differential voltage on the pair of state nodes.

    User interface system for display scaling events

    公开(公告)号:US11656732B2

    公开(公告)日:2023-05-23

    申请号:US17465740

    申请日:2021-09-02

    CPC classification number: G06F3/048 G06T3/40 G06F2203/04806

    Abstract: Systems, apparatuses, and methods for implementing enhanced scaling techniques for display objects are disclosed. When graphical content is created by an application, display objects register with a scaling manager to be notified of display scaling events. These display scaling events can be caused by changing displays, changing resolution or other parameters on a display, changing a text size, resizing one or more graphical elements, or otherwise. When a display scaling event is detected, display objects are notified of the event by the scaling manager. If a given display object makes a decision to change the amount of space it occupies based on the event, the given display object notifies its parent object of the desired change. The parent can then decide whether to allow the change and/or to make adjustments to other display objects to accommodate the change sought by the given display object.

Patent Agency Ranking