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公开(公告)号:US11669274B2
公开(公告)日:2023-06-06
申请号:US17218676
申请日:2021-03-31
Applicant: Advanced Micro Devices, Inc.
Inventor: Kedarnath Balakrishnan
IPC: G06F3/06
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0614 , G06F3/0653 , G06F3/0679
Abstract: A memory controller includes an arbiter for selecting memory requests from a command queue for transmission to a dynamic random access memory (DRAM) memory. The arbiter includes a bank group tracking circuit that tracks bank group numbers of three or more prior write requests selected by the arbiter. The arbiter also includes a selection circuit that selects requests to be issued from the command queue, and prevents selection of write requests and associated activate commands to the tracked bank group numbers unless no other write request is eligible in the command queue. The bank group tracking circuit indicates that a prior write request and the associated activate commands are eligible to be issued after a number of clock cycles has passed corresponding to a minimum write-to-write timing period for a bank group of the prior write request.
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公开(公告)号:US20230169728A1
公开(公告)日:2023-06-01
申请号:US17974199
申请日:2022-10-26
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor: Nishank PATHAK
CPC classification number: G06T17/20 , G06T15/005
Abstract: A processing system includes hull shader circuitry that launches thread groups including one or more primitives. The hull shader circuitry also generates tessellation factors that indicate subdivisions of the primitives. The processing system also includes throttling circuitry that estimates a primitive launch time interval for the domain shader based on the tessellation factors and selectively throttles launching of the thread groups from the hull shader circuitry based on the primitive launch time interval of the domain shader and a hull shader latency. In some cases, the throttling circuitry includes a first counter that is incremented in response to launching a thread group from the buffer and a second counter that modifies the first counter based on a measured latency of the domain shader.
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公开(公告)号:US11664062B2
公开(公告)日:2023-05-30
申请号:US16938855
申请日:2020-07-24
Applicant: Advanced Micro Devices, Inc.
Inventor: Jing Wang , Kedarnath Balakrishnan , Kevin M. Brandl , James R. Magro
IPC: G06F9/00 , G11C11/406 , G06F9/4401 , G06F1/3203
CPC classification number: G11C11/40611 , G06F1/3203 , G06F9/442 , G11C11/40615 , G06F9/4401
Abstract: A method for performing stutter of dynamic random access memory (DRAM) where a system on a chip (SOC) initiates bursts of requests to the DRAM to fill buffers to allow the DRAM to self-refresh is disclosed. The method includes issuing, by a system management unit (SMU), a ForceZQCal command to the memory controller to initiate the stutter procedure in response to receiving a timeout request, such as an SMU ZQCal timeout request, periodically issuing a power platform threshold (PPT) request, by the SMU, to the memory controller, and sending a ForceZQCal command prior to a PPT request to ensure re-training occurs after ZQ Calibration. The ForceZQCal command issued prior to PPT request may reduce the latency of the stutter. The method may further include issuing a ForceZQCal command prior to each periodic re-training.
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公开(公告)号:US11662798B2
公开(公告)日:2023-05-30
申请号:US17390479
申请日:2021-07-30
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor: Alexander J. Branover , Christopher T. Weaver , Benjamin Tsien , Indrani Paul , Mihir Shaileshbhai Doctor , Thomas J. Gibney , John P. Petry , Dennis Au , Oswin Hall
IPC: G06F1/32 , G06F1/3234 , G06F1/3209
CPC classification number: G06F1/3265 , G06F1/3209 , G06F1/3275
Abstract: A disclosed technique includes transmitting data in a first buffer associated with a first display pipe to a first display associated with the first display pipe; transmitting data in a second buffer associated with a second display pipe to the first display; requesting wake-up of a memory; and refilling one or both of the first buffer and the second buffer from the memory.
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公开(公告)号:US11658681B2
公开(公告)日:2023-05-23
申请号:US17348202
申请日:2021-06-15
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor: Greg Sadowski , John Kalamatianos
CPC classification number: H03M7/6047 , H03M5/04 , H04B1/04 , H04B1/16 , H04B3/54
Abstract: Various energy efficient data encoding schemes and computing devices are disclosed. In one aspect, a method of transmitting data from a transmitter to a receiver connected by plural wires is provided. The method includes sending from the transmitter on at least one but not all of the wires a first wave form that has first and second signal transitions. The receiver receives the first waveform and measures a first duration between the first and second signal transitions using a locally generated clock signal not received from the transmitter. The first duration is indicative of a first particular data value.
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公开(公告)号:US11657892B1
公开(公告)日:2023-05-23
申请号:US17561115
申请日:2021-12-23
Applicant: Advanced Micro Devices, Inc.
Inventor: Joel Thornton Irby , Grady L. Giles
CPC classification number: G11C29/4401 , G11C7/106 , G11C7/1012 , G11C7/1036 , G11C7/1087 , G11C29/1201 , G11C29/46 , G11C2029/1202
Abstract: An integrated circuit includes a latch array including a plurality of latches logically configured in rows and columns, a plurality of repair latches operatively coupled to the plurality of latches and latch array built in self-test and repair logic (LABISTRL) coupled to the plurality of latches. In some implementations the LABISTRL configures latches in the array as one or more column serial test shift register, detects one or more defective latches of the plurality of latches based on applied test data, and selects at least one repair latch in response to detection of at least one defective latch.
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公开(公告)号:US11657856B2
公开(公告)日:2023-05-23
申请号:US17113346
申请日:2020-12-07
Applicant: Advanced Micro Devices, Inc.
Inventor: Milam Paraschou , Jeffrey Cooper
CPC classification number: G11C7/065 , G11C15/04 , G11C2207/063
Abstract: Systems, apparatuses, and methods for implementing a sampling circuit with increased headroom are disclosed. A sampling circuit includes at least a pair of input signal transistors connected via their drains to a cross-coupled pair of state nodes. The cross-coupled pair of state nodes are coupled to a tail transistor device via the sources of N-type transistors. When clock goes low, the circuit precharges the cross-coupled pair of state nodes while simultaneously attempting to amplify the difference between the pair of input signals. The amplification is performed by a pair of transistors in series between a source of each input signal transistor and ground. Each gate of the pair of transistors is connected to an inverted clock signal. When clock goes high, the circuit stops precharging and a voltage difference between the pair of input signals is regenerated to create a resulting differential voltage on the pair of state nodes.
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公开(公告)号:US11656945B2
公开(公告)日:2023-05-23
申请号:US17133843
申请日:2020-12-24
Applicant: Advanced Micro Devices, Inc.
Inventor: John Kalamatianos , Nuwan Jayasena , Sudhanva Gurumurthi , Shaizeen Aga , Shrikanth Ganapathy
CPC classification number: G06F11/141 , G06F9/3877
Abstract: Methods and processing devices are provided for error protection to support instruction replay for executing idempotent instructions at a processing in memory PIM device. The processing apparatus includes a PIM device configured to execute an idempotent instruction. The processing apparatus also includes a processor, in communication with the PIM device, configured to issue the idempotent instruction to the PIM device for execution at the PIM device and reissue the idempotent instruction to the PIM device when one of execution of the idempotent instruction at the PIM device results in an error and a predetermined latency period expires from when the idempotent instruction is issued.
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公开(公告)号:US11656732B2
公开(公告)日:2023-05-23
申请号:US17465740
申请日:2021-09-02
Applicant: Advanced Micro Devices, Inc.
Inventor: Peter James Lohrmann
CPC classification number: G06F3/048 , G06T3/40 , G06F2203/04806
Abstract: Systems, apparatuses, and methods for implementing enhanced scaling techniques for display objects are disclosed. When graphical content is created by an application, display objects register with a scaling manager to be notified of display scaling events. These display scaling events can be caused by changing displays, changing resolution or other parameters on a display, changing a text size, resizing one or more graphical elements, or otherwise. When a display scaling event is detected, display objects are notified of the event by the scaling manager. If a given display object makes a decision to change the amount of space it occupies based on the event, the given display object notifies its parent object of the desired change. The parent can then decide whether to allow the change and/or to make adjustments to other display objects to accommodate the change sought by the given display object.
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公开(公告)号:US20230156250A1
公开(公告)日:2023-05-18
申请号:US18094161
申请日:2023-01-06
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor: Lei Zhang , Gabor Sines , Khaled Mammou , David Glen , Layla A. Mah , Rajabali M. Koduri , Bruce Montag
IPC: H04N21/2343 , H04N21/2368 , H04N21/236 , H04N21/414 , H04N21/422 , H04N21/434 , H04N21/437 , H04L69/24 , H04N21/43 , H04L65/70 , H04L65/75 , H04L67/131
CPC classification number: H04N21/2343 , H04N21/2368 , H04N21/23605 , H04N21/41407 , H04N21/42202 , H04N21/4341 , H04N21/437 , H04N21/4343 , H04L69/24 , H04N21/43072 , H04L65/70 , H04L65/762 , H04L67/131
Abstract: Virtual Reality (VR) processing devices and methods are provided for transmitting user feedback information comprising at least one of user position information and user orientation information, receiving encoded audio-video (AN) data, which is generated based on the transmitted user feedback information, separating the A/V data into video data and audio data corresponding to a portion of a next frame of a sequence of frames of the video data to be displayed, decoding the portion of a next frame of the video data and the corresponding audio data, providing the audio data for aural presentation and controlling the portion of the next frame of the video data to be displayed in synchronization with the corresponding audio data.
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