公开(公告)号：US20200050561A1

公开(公告)日：2020-02-13

申请号：US16546694

申请日：2019-08-21

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Amir Amirkhany ,  Suresh Rajan ,  Mohammad Hekmat ,  Dinesh Patil

IPC: G06F13/16 ,  G06F13/40 ,  G11C7/10 ,  G11C5/02 ,  G11C11/4096 ,  G11C11/4093 ,  G11C11/4076 ,  G11C7/22 ,  G11C11/419 ,  G11C8/18

Abstract: A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.

公开(公告)号：US10558520B2

公开(公告)日：2020-02-11

申请号：US15838161

申请日：2017-12-11

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Craig E. Hampel

IPC: G06F11/00 ,  G06F11/10 ,  G06F11/07 ,  G06F11/16 ,  H03M13/09

Abstract: Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a memory operation.

公开(公告)号：US10541693B2

公开(公告)日：2020-01-21

申请号：US16242475

申请日：2019-01-08

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Brian S. Leibowitz ,  Hsuan-Jung Su ,  John Cronan Eble, III ,  Barry William Daly ,  Lei Luo ,  Teva J. Stone ,  John Wilson ,  Jihong Ren ,  Wayne D. Dettloff

IPC: H03L7/091 ,  H03K5/156 ,  H03L7/00 ,  G11C7/10 ,  G11C7/22 ,  H04L7/00 ,  H04L7/033 ,  H03L7/08 ,  H03L7/099 ,  G11C7/04

Abstract: A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.

公开(公告)号：US10536304B2

公开(公告)日：2020-01-14

申请号：US15670916

申请日：2017-08-07

Applicant: Rambus Inc.

Inventor： Qi Lin ,  Brian Leibowitz ,  Hae-Chang Lee ,  Jihong Ren ,  Kyung Suk Oh ,  Jared L. Zerbe

IPC: H04L25/03 ,  H04L7/00 ,  H04L7/033 ,  H04L12/26

Abstract: A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.

公开(公告)号：US20200012332A1

公开(公告)日：2020-01-09

申请号：US16418259

申请日：2019-05-21

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Robert E. Palmer ,  John W. Poulton ,  Andrew M. Fuller

IPC: G06F1/3237 ,  G06F3/06 ,  G06F1/324 ,  G06F1/3225 ,  G06F1/12 ,  G11C7/22 ,  G06F13/16 ,  G11C11/4096 ,  G11C11/4076 ,  G11C7/10 ,  G11C7/04

Abstract: A memory controller component of a memory system stores memory access requests within a transaction queue until serviced so that, over time, the transaction queue alternates between occupied and empty states. The memory controller transitions the memory system to a low power mode in response to detecting the transaction queue is has remained in the empty state for a predetermined time. In the transition to the low power mode, the memory controller disables oscillation of one or more timing signals required to time data signaling operations within synchronous communication circuits of one or more attached memory devices and also disables one or more power consuming circuits within the synchronous communication circuits of the one or more memory devices.

公开(公告)号：US10522194B2

公开(公告)日：2019-12-31

申请号：US16148491

申请日：2018-10-01

Applicant: Rambus Inc.

Inventor： Scott C. Best ,  John W. Poulton

IPC: H04B15/00 ,  G11C5/14 ,  H04L25/02 ,  G06F13/40 ,  H04L1/20 ,  H04L25/08 ,  G06F11/07

Abstract: In a data transmission system, one or more signal supply voltages for generating the signaling voltage of a signal to be transmitted are generated in a first circuit and forwarded from the first circuit to a second circuit. The second circuit may use the forwarded signal supply voltages to generate another signal to be transmitted back from the second circuit to the first circuit, thereby obviating the need to generate signal supply voltages separately in the second circuit. The first circuit may also adjust the signal supply voltages based on the signal transmitted back from the second circuit to the first circuit. The data transmission system may employ a single-ended signaling system in which the signaling voltage is referenced to a reference voltage that is a power supply voltage such as ground, shared by the first circuit and the second circuit.

公开(公告)号：US20190394071A1

公开(公告)日：2019-12-26

申请号：US16441692

申请日：2019-06-14

Applicant: Rambus Inc.

Inventor： Kamran FARZAN ,  Aaron ALI

IPC: H04L25/49 ,  H03H7/38 ,  H04L25/02

Abstract: A hybrid voltage mode (VM) and current mode (CM) four-level pulse amplitude modulation (PAM-4) transmitter circuits (a.k.a. drivers) is calibrated using a configurable replica circuit and calibration control circuitry. The replica circuit includes an on-chip termination impedance to mimic a receiver's termination impedance. The amount of level enhancement provided by the current mode circuitry is calibrated by adjusting the current provided to the output node and sunk from the output node by the replica current mode circuitry while the replica voltage mode circuitry is driving an intermediate PAM-4 level. After the level enhancement has been set, the non-linearity between levels is calibrated by adjusting the amount of current provided to the output node by the replica current mode circuitry while the replica voltage mode circuitry is driving a maximum output voltage level.

公开(公告)号：US10510388B2

公开(公告)日：2019-12-17

申请号：US16174180

申请日：2018-10-29

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Kyung Suk Oh

IPC: G11C5/06 ,  G11C7/22 ,  G11C29/02 ,  G11C11/4063 ,  G11C5/04 ,  G11C11/4097 ,  G11C7/18 ,  G11C5/02

Abstract: A system has a plurality of memory devices arranged in a fly-by topology, each having on-die termination (ODT) circuitry for connecting to an address and control (RQ) bus. The ODT circuitry of each memory device includes a set of one or more control registers for controlling on-die termination of one or more signal lines of the RQ bus. A first memory device includes a first set of one or more control registers storing a first ODT value, for controlling termination of one or more signal lines of the RQ bus by the ODT circuitry of the first memory device, and a second memory device includes a second set of one or more control registers storing a second ODT value different from the first ODT value, for controlling termination of one or more signal lines of the RQ bus by the ODT circuitry of the second memory device.

公开(公告)号：US10509741B2

公开(公告)日：2019-12-17

申请号：US16145837

申请日：2018-09-28

Applicant: Rambus Inc.

Inventor： Pravin Kumar Venkatesan ,  Liji Gopalakrishnan ,  Kashinath Ullhas Prabhu ,  Makarand Ajit Shirasgaonkar

IPC: G06F13/16

Abstract: A single-ended receiver is coupled to an input-output (I/O) pin of a command and address (CA) bus. The receiver is configurable with dual-mode I/O support to operate the CA bus in a low-swing mode and a high-swing mode. The receiver is configurable to receive a first command on the I/O pin while in the high-swing mode, initiate calibration of the slave device to operate in the low-swing mode in response to the first command, switch the slave device to operate in the low-swing mode while the CA bus remains active, and to receive a second command on the I/O pin while in the low-swing mode.

公开(公告)号：US10509448B2

公开(公告)日：2019-12-17

申请号：US15243596

申请日：2016-08-22

Applicant: RAMBUS INC.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Patrick R. Gill

IPC: G06F1/20 ,  F25B49/00 ,  G06F1/26 ,  H05K7/20 ,  H01B12/02 ,  H01R4/68 ,  H01L39/02 ,  H02G15/34

Abstract: The embodiments herein describe technologies of cryogenic digital systems with a power supply located in an ambient temperature domain and logic located in a cryogenic temperature domain. A pair of conductors is operable to carry current with a voltage difference between the power supply and the logic. The pair of conductors includes a first portion thermally coupled to a temperature-regulated or temperature-controlled intermediate temperature domain. The intermediate temperature domain is less than the ambient temperature domain and greater than the cryogenic temperature domain.