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    LATE GATE CUT USING SELECTIVE DIELECTRIC DEPOSITION
    291.
    发明申请
    LATE GATE CUT USING SELECTIVE DIELECTRIC DEPOSITION 审中-公开

    公开(公告)号：US20200168509A1

    公开(公告)日：2020-05-28

    申请号：US16201449

    申请日：2018-11-27

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Hui Zang ,  Ruilong Xie ,  Jiehui Shu ,  Chanro Park ,  Laertis Economikos

    IPC: H01L21/8234 ,  H01L21/311 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/02 ,  H01L21/033 ,  H01L29/423 ,  H01L27/088

    Abstract: Methods of forming a structure that includes field-effect transistor and structures that include a field effect-transistor. A dielectric cap is formed over a gate structure of a field-effect transistor, and an opening is patterned that extends fully through the dielectric cap to divide the dielectric cap into a first section and a second section spaced across the opening from the first surface. First and second dielectric spacers are respectively selectively deposited on respective first and second surfaces of the first and second sections of the dielectric cap to shorten the opening. A portion of the gate structure exposed through the opening between the first and second dielectric spacers is etched to form a cut that divides the gate electrode into first and second sections disconnected by the cut. A dielectric material is deposited in the opening and in the cut to form a dielectric pillar.

    INTEGRATED GATE CONTACT AND CROSS-COUPLING CONTACT FORMATION
    293.
    发明申请
    INTEGRATED GATE CONTACT AND CROSS-COUPLING CONTACT FORMATION 审中-公开

    公开(公告)号：US20200152518A1

    公开(公告)日：2020-05-14

    申请号：US16185675

    申请日：2018-11-09

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Hui Zang ,  Ruilong Xie ,  Chanro Park ,  Laertis Economikos

    IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/417 ,  H01L29/423 ,  H01L21/768 ,  H01L29/40

    Abstract: Methods of forming cross-coupling contacts for field-effect transistors and structures for field effect-transistors that include cross-coupling contacts. A dielectric cap is formed over a gate structure and a sidewall spacer adjacent to a sidewall of the gate structure. A portion of the dielectric cap is removed from over the sidewall spacer and the gate structure to expose a first portion of the gate electrode of the gate structure at a top surface of the gate structure. The sidewall spacer is then recessed relative to the gate structure to expose a portion of the gate dielectric layer at the sidewall of the gate structure, which is removed to expose a second portion of the gate electrode of the gate structure. A cross-coupling contact is formed that connects the first and second portions of the gate electrode of the gate structure with an epitaxial semiconductor layer adjacent to the sidewall spacer.

    Inner spacer formation in a nanosheet field-effect transistor
    294.
    发明授权
    Inner spacer formation in a nanosheet field-effect transistor 有权

    公开(公告)号：US10651291B2

    公开(公告)日：2020-05-12

    申请号：US15680467

    申请日：2017-08-18

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Julien Frougier ,  Ruilong Xie

    IPC: H01L29/20 ,  H01L29/16 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/423 ,  H01L29/10 ,  H01L29/08 ,  H01L21/223 ,  H01L21/311 ,  H01L29/775 ,  B82Y10/00 ,  H01L29/40 ,  H01L29/786

    Abstract: Structures for a nanosheet field-effect transistor and methods for forming a structure for a nanosheet field-effect transistor. A body feature is formed that includes a sacrificial layer arranged vertically between the first and second nanosheet channel layers. The sacrificial layer is laterally recessed at a sidewall of the body feature to expose respective portions of the first and second nanosheet channel layers. A sacrificial spacer is formed by oxidizing a portion of the sacrificial layer at the sidewall of the body feature. Sections of a semiconductor material are epitaxially grown on the exposed portions of the first and second nanosheet channel layers to narrow a gap vertically separating the first and second nanosheet channel layers. The sacrificial spacer is removed to form a cavity between the sections of the semiconductor material and the sacrificial layer. A dielectric spacer is conformally deposited in the cavity.

    INTEGRATED CIRCUIT STRUCTURE WITH COMPLEMENTARY FIELD EFFECT TRANSISTOR AND BURIED METAL INTERCONNECT AND METHOD
    296.
    发明申请
    INTEGRATED CIRCUIT STRUCTURE WITH COMPLEMENTARY FIELD EFFECT TRANSISTOR AND BURIED METAL INTERCONNECT AND METHOD 审中-公开

    公开(公告)号：US20200111798A1

    公开(公告)日：2020-04-09

    申请号：US16152454

    申请日：2018-10-05

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Bipul C. Paul ,  Ruilong Xie

    IPC: H01L27/11 ,  H01L23/528 ,  H01L21/768

    Abstract: Disclosed are structures with a complementary field effect transistor (CFET) and a buried metal interconnect that electrically connects a source/drain region of a lower-level transistor of the CFET with another device. The structure can include a memory cell with first and second CFETs, where each CFET includes a pull-up transistor stacked on and having a common gate with a pull-down transistor and each pull-down transistor has a common source/drain region with a pass-gate transistor. The metal interconnect connects a lower-level source/drain region of the first CFET (i.e., the common source/drain region of first pass-gate and pull-up transistors) to the common gate of the second CFET (i.e., to the common gate of second pull-down and pull-up transistors). Formation methods include forming an interconnect placeholder during lower-level source/drain region formation. After upper-level source/drain regions and replacement metal gates are formed, the interconnect placeholder is exposed, removed and replaced with a metal interconnect.

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