公开(公告)号：US11847557B2

公开(公告)日：2023-12-19

申请号：US17885437

申请日：2022-08-10

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Vipin Tiwari ,  Nhan Do

IPC: G11C11/56 ,  G06N3/065 ,  G06F3/06 ,  G06F17/16 ,  G06N3/08 ,  G11C13/00 ,  G11C16/04 ,  G11C16/28 ,  G06N3/048

CPC classification number: G06N3/065 ,  G06F3/061 ,  G06F3/0688 ,  G06F17/16 ,  G06N3/048 ,  G06N3/08 ,  G11C11/5642 ,  G11C13/004 ,  G11C16/0425 ,  G11C16/28 ,  G11C2211/563 ,  G11C2213/15

Abstract: Numerous embodiments are disclosed for compensating for differences in the slope of the current-voltage characteristic curve among reference transistors, reference memory cells, and flash memory cells during a read operation in an analog neural memory in a deep learning artificial neural network. In one embodiment, a method comprises receiving an input voltage, multiplying the input voltage by a coefficient to generate an output voltage, applying the output voltage to a gate of a selected memory cell, performing a sense operating using the selected memory cell and a reference device to determine a value stored in the selected memory cell, wherein a slope of a current-voltage characteristic curve of the reference device and a slope of the current-voltage characteristic curve of the selected memory cell are approximately equal during the sense operation.

公开(公告)号：US11829859B2

公开(公告)日：2023-11-28

申请号：US17233006

申请日：2021-04-16

Applicant: Silicon Storage Technology, Inc. ,  The Regents of the University of California

Inventor： Farnood Merrikh Bayat ,  Xinjie Guo ,  Dmitri Strukov ,  Nhan Do ,  Hieu Van Tran ,  Vipin Tiwari ,  Mark Reiten

IPC: G06N3/04 ,  G06N3/063 ,  G11C11/54 ,  G11C16/34 ,  G11C29/38 ,  G06N3/045 ,  G11C16/08 ,  G11C16/12 ,  G11C16/16 ,  G06F3/06

CPC classification number: G06N3/04 ,  G06F3/061 ,  G06F3/0655 ,  G06F3/0688 ,  G06N3/045 ,  G06N3/063 ,  G11C11/54 ,  G11C16/08 ,  G11C16/12 ,  G11C16/16 ,  G11C16/3436 ,  G11C29/38

Abstract: Numerous embodiments are disclosed for verifying a weight programmed into a selected non-volatile memory cell in a neural memory. In one embodiment, a circuit for verifying a weight programmed into a selected non-volatile memory cell in a neural memory comprises a converter for converting a target weight into a target current and a comparator for comparing the target current to an output current from the selected non-volatile memory cell during a verify operation. In another embodiment, a circuit for verifying a weight programmed into a selected non-volatile memory cell in a neural memory comprises a digital-to-analog converter for converting a target weight comprising digital bits into a target voltage, a current-to-voltage converter for converting an output current from the selected non-volatile memory cell during a verify operation into an output voltage, and a comparator for comparing the output voltage to the target voltage during a verify operation.

公开(公告)号：US20230368011A1

公开(公告)日：2023-11-16

申请号：US18227254

申请日：2023-07-27

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Steven Lemke ,  Vipin Tiwari ,  Nhan Do ,  Mark Reiten

IPC: G06N3/065 ,  G06F17/16 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34 ,  G11C16/26 ,  G11C11/56 ,  G11C16/14 ,  G06N3/044

CPC classification number: G06N3/065 ,  G06F17/16 ,  G11C16/0425 ,  G11C16/10 ,  G11C16/3459 ,  G11C16/26 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/14 ,  G06N3/044 ,  G11C2216/04

Abstract: In one example, a method comprises performing a first programming process on a selected non-volatile memory cell, the first programming process comprising a plurality of program-verify cycles, wherein a programming voltage duration of increasing period is applied to one of a floating gate, a control gate terminal, an erase gate terminal, and a source line terminal of the selected non-volatile memory cell in each program-verify cycle after the first program-verify cycle.

公开(公告)号：US20230325646A1

公开(公告)日：2023-10-12

申请号：US17848381

申请日：2022-06-23

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  THUAN VU ,  STANLEY HONG ,  STEPHEN TRINH ,  STEVEN LEMKE ,  LOUISA SCHNEIDER ,  NHAN DO

IPC: G06N3/063

CPC classification number: G06N3/063

Abstract: Numerous examples are disclosed of an artificial neural network comprising a plurality of reference arrays used for configuration of a vector-by-matrix multiplication array. In one example, a system comprises a vector-by-matrix multiplication array in an artificial neural network; and a plurality of reference arrays characterized by different I-V curves, wherein one or more of the plurality of reference arrays are used to generate input voltage the vector-by-matrix multiplication array during operation.

公开(公告)号：US20230268004A1

公开(公告)日：2023-08-24

申请号：US18140103

申请日：2023-04-27

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Stanley Hong ,  Stephen Trinh ,  Thuan Vu ,  Steven Lemke ,  Vipin Tiwari ,  Nhan Do

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/34 ,  G11C11/56 ,  G11C16/14 ,  G06N3/065

CPC classification number: G11C16/10 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/3459 ,  G11C11/5628 ,  G11C16/14 ,  G06N3/065

Abstract: In one example, a method comprises determining a program resolution current value; and setting levels for a programming operation of a plurality of non-volatile memory cells in a neural network array such that a delta current between levels of each pair of adjacent cells in the plurality is a multiple of the program resolution current value.

公开(公告)号：US20230229903A1

公开(公告)日：2023-07-20

申请号：US18125703

申请日：2023-03-23

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stanley Hong ,  Stephen Trinh ,  Anh Ly

IPC: G06N3/00 ,  G11C11/54 ,  G11C7/10 ,  G11C8/10 ,  G11C7/12

CPC classification number: G06N3/065 ,  G11C11/54 ,  G11C7/1069 ,  G11C7/1096 ,  G11C8/10 ,  G11C7/12

Abstract: Numerous embodiments are disclosed for splitting a physical array into multiple arrays for separate vector-by-matrix multiplication (VMM) operations. In one example, a system comprises an array of non-volatile memory cells arranged into rows and columns; and a plurality of sets of output lines, where each column contains a set of output lines; wherein each row is coupled to only one output line in the set of output lines for each column.

公开(公告)号：US20230229888A1

公开(公告)日：2023-07-20

申请号：US18123921

申请日：2023-03-20

Applicant: Silicon Storage Technology, Inc. ,  The Regents of the University of California

Inventor： Farnood Merrikh Bayat ,  Xinjie Guo ,  Dmitri Strukov ,  Nhan Do ,  Hieu Van Tran ,  Vipin Tiwari ,  Mark Reiten

IPC: G06N3/04 ,  G06N3/063 ,  G11C11/54 ,  G11C16/34 ,  G11C29/38 ,  G06N3/045 ,  G11C16/08 ,  G11C16/12 ,  G11C16/16 ,  G06F3/06

CPC classification number: G06N3/04 ,  G06N3/063 ,  G11C11/54 ,  G11C16/3436 ,  G11C29/38 ,  G06N3/045 ,  G11C16/08 ,  G11C16/12 ,  G11C16/16 ,  G06F3/061 ,  G06F3/0655 ,  G06F3/0688

Abstract: Numerous examples of summing circuits for a neural network are disclosed. In one example, a circuit for summing current received from a plurality of synapses in a neural network comprises a voltage source; a load coupled between the voltage source and an output node; a voltage clamp coupled to the output node for maintaining a voltage at the output node; and a plurality of synapses coupled between the output node and ground; wherein an output current flows through the output node, the output current equal to a sum of currents drawn by the plurality of synapses.

公开(公告)号：US11646075B2

公开(公告)日：2023-05-09

申请号：US17471099

申请日：2021-09-09

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Steven Lemke ,  Vipin Tiwari ,  Nhan Do ,  Mark Reiten

IPC: G11C11/54 ,  H01L29/423 ,  G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  H01L29/788 ,  G06N3/045

CPC classification number: G11C11/54 ,  G06N3/045 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/7883 ,  H10B41/30

Abstract: A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region disposed between source and drain regions, and a second gate over the floating gate or the source region. First lines each electrically connect the first gates in one of the memory cell rows, second lines each electrically connect the second gates in one of the memory cell rows, third lines each electrically connect the source regions in one of the memory cell columns, and fourth lines each electrically connect the drain regions in one of the memory cell columns. The synapses receive a first plurality of inputs as electrical voltages on the first or second lines, and provide a first plurality of outputs as electrical currents on the third or fourth lines.

公开(公告)号：US11636322B2

公开(公告)日：2023-04-25

申请号：US16829757

申请日：2020-03-25

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Steven Lemke ,  Vipin Tiwari ,  Nhan Do ,  Mark Reiten

IPC: G06N3/063 ,  G11C11/54 ,  G06F1/03 ,  G06F17/16 ,  G11C11/56 ,  G06F11/16 ,  G11C13/00 ,  G11C29/44 ,  G06F7/78

Abstract: Numerous embodiments of a precision programming algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. Selected cells thereby can be programmed with extreme precision to hold one of N different values.

公开(公告)号：US20230031487A1

公开(公告)日：2023-02-02

申请号：US17949962

申请日：2022-09-21

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Steven Lemke ,  Vipin Tiwari ,  Nhan Do ,  Mark Reiten

IPC: H01L27/11531 ,  G11C16/04 ,  G06N3/08 ,  H01L29/788

Abstract: Numerous examples of an input function circuit block and an output neuron circuit block coupled to a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. In one example, an artificial neural network comprises a vector-by-matrix multiplication array comprising a plurality of non-volatile memory cells organized into rows and columns; an input function circuit block to receive digital input signals, convert the digital input signals into analog signals, and apply the analog signals to control gate terminals of non-volatile memory cells in one or more rows of the array during a programming operation; and an output neuron circuit block to receive analog currents from the columns of the array during a read operation and generate an output signal.