公开(公告)号：US20170317093A1

公开(公告)日：2017-11-02

申请号：US15476663

申请日：2017-03-31

Applicant: Silicon Storage Technology, Inc.

Inventor： Chunming Wang ,  Nhan Do

IPC: H01L27/11521 ,  G11C16/10 ,  G11C16/16 ,  H01L29/423

CPC classification number: H01L27/11521 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/16 ,  H01L21/28273 ,  H01L27/11524 ,  H01L29/42328

Abstract: A memory device that includes a substrate of semiconductor material of a first conductivity type, first and second regions spaced apart in the substrate and having a second conductivity type different than the first conductivity type, with a continuous channel region in the substrate extending between the first and second regions. A first floating gate is disposed over and insulated from a first portion of the channel region adjacent to the first region. A second floating gate is disposed over and insulated from a second portion of the channel region adjacent to the second region. A word line gate is disposed over and insulated from a third portion of the channel region between the first and second channel region portions. A first erase gate disposed over and insulated from the first region. A second erase gate disposed is over and insulated from the second region.

公开(公告)号：US20170316823A1

公开(公告)日：2017-11-02

申请号：US15404087

申请日：2017-01-11

Applicant: Silicon Storage Technology, Inc. ,  Agency For Science, Technology And Research

Inventor： Feng Zhou ,  XIAN LIU ,  NHAN DO ,  HIEU VAN TRAN ,  HUNG QUOC NGUYEN ,  MARK REITEN ,  ZHIXIAN CHEN ,  WANG XINPENG ,  GUO-QIANG LO

IPC: G11C13/00 ,  H01L45/00

CPC classification number: G11C13/0007 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16

Abstract: A memory device and method comprising a metal oxide material disposed between and in electrical contact with first and second conductive electrodes, and a voltage source configured to apply a plurality of voltage pulses spaced apart in time across the first and second electrodes. For each one of the voltage pulses, an amplitude of the voltage increases during the voltage pulse.

公开(公告)号：US09793281B2

公开(公告)日：2017-10-17

申请号：US15180376

申请日：2016-06-13

Applicant: Silicon Storage Technology, Inc.

Inventor： Chien-Sheng Su ,  Jeng-Wei Yang ,  Feng Zhou

IPC: H01L27/115 ,  H01L27/11531 ,  H01L27/11524 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L27/11521

CPC classification number: H01L27/11531 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42328 ,  H01L29/66484 ,  H01L29/66825 ,  H01L29/7881

Abstract: A method of forming split gate non-volatile memory cells on the same chip as logic and high voltage devices having HKMG logic gates. The method includes forming the source and drain regions, floating gates, control gates, and the poly layer for the erase gates and word line gates in the memory area of the chip. A protective insulation layer is formed over the memory area, and an HKMG layer and poly layer are formed on the chip, removed from the memory area, and patterned in the logic areas of the chip to form the logic gates having varying amounts of underlying insulation.

公开(公告)号：US09793279B2

公开(公告)日：2017-10-17

申请号：US15182527

申请日：2016-06-14

Applicant: Silicon Storage Technology, Inc.

Inventor： Jeng-Wei Yang ,  Man-Tang Wu ,  Chun-Ming Chen ,  Mandana Tadayoni ,  Chien-Sheng Su ,  Nhan Do

IPC: H01L27/115 ,  H01L27/11524 ,  H01L29/423 ,  H01L21/28 ,  H01L29/788 ,  H01L29/66 ,  G11C16/26 ,  H01L27/11521

CPC classification number: H01L27/11524 ,  G11C16/26 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/7883

Abstract: A memory device including a silicon semiconductor substrate, spaced apart source and drain regions formed in the substrate with a channel region there between, and a conductive floating gate disposed over a first portion of the channel region and a first portion of the source region. An erase gate includes a first portion that is laterally adjacent to the floating gate and over the source region, and a second portion that extends up and over the floating gate. A conductive word line gate is disposed over a second portion of the channel region. The word line gate is disposed laterally adjacent to the floating gate and includes no portion disposed over the floating gate. The thickness of insulation separating the word line gate from the second portion of the channel region is less than that of insulation separating the floating gate from the erase gate.

公开(公告)号：US09767911B2

公开(公告)日：2017-09-19

申请号：US14791213

申请日：2015-07-02

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen

IPC: G11C16/12 ,  G11C16/24 ,  G11C16/08 ,  G11C16/10 ,  G11C16/30

CPC classification number: G11C16/12 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/30

Abstract: An improved method and apparatus for programming advanced nanometer flash memory cells is disclosed.

公开(公告)号：US09646700B2

公开(公告)日：2017-05-09

申请号：US14449926

申请日：2014-08-01

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Hung Quoc Nguyen ,  Anh Ly ,  Thuan Vu

IPC: G11C16/10 ,  H01L27/11517 ,  G11C16/26 ,  G11C7/00 ,  G11C16/28 ,  G11C7/22

CPC classification number: G11C16/10 ,  G11C7/00 ,  G11C7/22 ,  G11C16/26 ,  G11C16/28 ,  G11C2207/2263 ,  G11C2211/5647 ,  H01L27/11517

Abstract: A non-volatile memory device has a charge pump for providing a programming current and an array of non-volatile memory cells. Each memory cell of the array is programmed by the programming current from the charge pump. The array of non-volatile memory cells is partitioned into a plurality of units, with each unit comprising a plurality of memory cells. An indicator memory cell is associated with each unit of non-volatile memory cells. A programming circuit programs the memory cells of each unit using the programming current, when fifty percent or less of the memory cells of each unit is to be programmed, and programs the inverse of the memory cells of each unit and the indicator memory cell associated with each unit, using the programming current, when more than fifty percent of the memory cells of each unit is to be programmed.

公开(公告)号：US20170076809A1

公开(公告)日：2017-03-16

申请号：US15361473

申请日：2016-11-27

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen

IPC: G11C16/30 ,  H01L27/115 ,  G11C16/04 ,  G11C16/14 ,  G11C16/26

CPC classification number: G11C16/30 ,  G11C5/14 ,  G11C5/145 ,  G11C5/147 ,  G11C8/08 ,  G11C16/0408 ,  G11C16/0425 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/26 ,  G11C2216/04 ,  H01L27/11521

Abstract: A non-volatile memory device comprises a semiconductor substrate of a first conductivity type. An array of non-volatile memory cells is located in the semiconductor substrate and arranged in a plurality of rows and columns. Each memory cell comprises a first region on a surface of the semiconductor substrate of a second conductivity type, and a second region on the surface of the semiconductor substrate of the second conductivity type. A channel region is between the first region and the second region. A word line overlies a first portion of the channel region and is insulated therefrom, and adjacent to the first region and having little or no overlap with the first region. A floating gate overlies a second portion of the channel region, is adjacent to the first portion, and is insulated therefrom and is adjacent to the second region. A coupling gate overlies the floating gate. A bit line is connected to the first region. During the operations of program, read, or erase, a negative voltage can be applied to the word lines and/or coupling gates of the selected or unselected memory cells.

Abstract translation: 非易失性存储器件包括第一导电类型的半导体衬底。 非易失性存储单元的阵列位于半导体衬底中并且被布置成多个行和列。 每个存储单元包括第二导电类型的半导体衬底的表面上的第一区域和第二导电类型的半导体衬底的表面上的第二区域。 沟道区域在第一区域和第二区域之间。 字线覆盖在沟道区域的第一部分上，并且与第一区域绝缘，并且与第一区域相邻并且与第一区域几乎没有或没有重叠。 浮动栅极覆盖沟道区域的第二部分，与第一部分相邻，并与第二部分绝缘并与第二区域相邻。 耦合栅极覆盖浮栅。 位线连接到第一区域。 在程序，读取或擦除的操作期间，负电压可以被施加到所选择的或未选择的存储单元的字线和/或耦合门。

公开(公告)号：US20170012049A1

公开(公告)日：2017-01-12

申请号：US15182527

申请日：2016-06-14

Applicant: Silicon Storage Technology, Inc.

Inventor： Jeng-Wei Yang ,  Man-Tang Wu ,  Chun-Ming Chen ,  Mandana Tadayoni ,  Chien-Sheng Su ,  Nhan Do

IPC: H01L27/115 ,  G11C16/26 ,  H01L29/788 ,  H01L29/66 ,  H01L29/423 ,  H01L21/28

CPC classification number: H01L27/11524 ,  G11C16/26 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/7883

Abstract: A memory device including a silicon semiconductor substrate, spaced apart source and drain regions formed in the substrate with a channel region there between, and a conductive floating gate disposed over a first portion of the channel region and a first portion of the source region. An erase gate includes a first portion that is laterally adjacent to the floating gate and over the source region, and a second portion that extends up and over the floating gate. A conductive word line gate is disposed over a second portion of the channel region. The word line gate is disposed laterally adjacent to the floating gate and includes no portion disposed over the floating gate. The thickness of insulation separating the word line gate from the second portion of the channel region is less than that of insulation separating the floating gate from the erase gate.

Abstract translation: 一种存储器件，包括硅半导体衬底，形成在衬底中的间隔开的源极和漏极区域，其间具有沟道区域，以及布置在沟道区域的第一部分和源极区域的第一部分之间的导电浮动栅极。 擦除栅极包括横向邻近浮动栅极并在源极区域上方的第一部分，以及在浮动栅极上方和上方延伸的第二部分。 导电字线栅极设置在沟道区域的第二部分上。 字线栅极横向地布置在浮动栅极附近，并且不包括设置在浮动栅极上的部分。 将字线栅极与沟道区域的第二部分分开的绝缘层的厚度小于将浮栅与擦除栅极分开的绝缘层的厚度。

公开(公告)号：US20160293260A1

公开(公告)日：2016-10-06

申请号：US15048707

申请日：2016-02-19

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen

IPC: G11C16/14 ,  G11C16/04 ,  G11C16/26

CPC classification number: G11C16/14 ,  G11C16/04 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3427

Abstract: Various embodiments for inhibiting the programming of memory cells coupled to unselected bit lines while programming a memory cell coupled to a selected bit line in a flash memory array are disclosed. Various embodiments for compensating for leakage current during the programming of memory cells coupled to a selected bit line in a flash memory array also are disclosed.

Abstract translation: 公开了用于禁止耦合到未选位线的存储器单元的编程，同时编程耦合到快闪存储器阵列中的选定位线的存储器单元的各种实施例。 还公开了用于在与存储器阵列中的选定位线耦合的存储器单元的编程期间补偿泄漏电流的各种实施例。

公开(公告)号：US20160254269A1

公开(公告)日：2016-09-01

申请号：US14639063

申请日：2015-03-04

Applicant: Silicon Storage Technology, Inc.

Inventor： Jinho Kim ,  Vipin Tiwari ,  Nhan Do ,  Xian Liu ,  Xiaozhou Qian ,  Ning Bai ,  Kai Man Yue

IPC: H01L27/115 ,  H01L29/788 ,  H01L29/423

CPC classification number: H01L27/11524 ,  H01L23/57 ,  H01L27/11226 ,  H01L27/11233 ,  H01L27/11253 ,  H01L27/11519 ,  H01L29/42328 ,  H01L29/788 ,  H01L29/7881

Abstract: A memory device that includes a plurality of ROM cells each having spaced apart source and drain regions formed in a substrate with a channel region therebetween, a first gate disposed over and insulated from a first portion of the channel region, a second gate disposed over and insulated from a second portion of the channel region, and a conductive line extending over the plurality of ROM cells. The conductive line is electrically coupled to the drain regions of a first subgroup of the ROM cells, and is not electrically coupled to the drain regions of a second subgroup of the ROM cells. Alternately, a first subgroup of the ROM cells each includes a higher voltage threshold implant region in the channel region, whereas a second subgroup of the ROM cells each lack any higher voltage threshold implant region in the channel region.

Abstract translation: 一种存储器件，其包括多个ROM单元，每个ROM单元具有形成在衬底中的间隔开的源极和漏极区域，其间具有沟道区域，设置在沟道区域的第一部分上方并与沟道区域的第一部分绝缘的第一栅极， 与沟道区的第二部分绝缘，以及在多个ROM单元上延伸的导电线。 导电线电耦合到ROM单元的第一子组的漏极区域，并且不电耦合到ROM单元的第二子组的漏极区域。 或者，ROM单元的第一子组各自包括沟道区域中的较高电压阈值注入区域，而ROM单元的第二子组每个在沟道区域中都缺少任何较高电压阈值注入区域。