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    Content addressable memory decomposition
    331.
    发明授权
    Content addressable memory decomposition 有权

    公开(公告)号：US09899088B1

    公开(公告)日：2018-02-20

    申请号：US14862750

    申请日：2015-09-23

    Applicant: Xilinx, Inc.

    Inventor： Weirong Jiang

    IPC: G06F12/00 ,  G11C15/04 ,  G06F3/06 ,  G06F12/0802 ,  G06F12/0864

    CPC classification number: G11C15/046 ,  G06F3/0626 ,  G06F3/0638 ,  G06F12/0802 ,  G06F12/0864 ,  G11C7/1006 ,  G11C15/00

    Abstract: Circuits and methods are disclosed for decomposition of a content addressable memory into a plurality of CAMs having a lower cost. In an example implementation, a set of CAM rules are grouped into a plurality of subsets. For each of the subsets, CAM rules in the subset are reformatted for storage in a respective CAM configured to store fewer ternary bits or configured for prefix match. Each reformatted subset of CAM rules are stored in the respective CAM. A search key formatting circuit is configured to reformat an input search key for each of the respective CAMs is used to store the reformatted subsets to produce a respective reformatted search key and input the respective reformatted search key to the respective CAM.

    BINARY NEURAL NETWORKS ON PROGAMMABLE INTEGRATED CIRCUITS
    332.
    发明申请
    BINARY NEURAL NETWORKS ON PROGAMMABLE INTEGRATED CIRCUITS 审中-公开

    公开(公告)号：US20180039886A1

    公开(公告)日：2018-02-08

    申请号：US15230164

    申请日：2016-08-05

    Applicant: Xilinx, Inc.

    Inventor： Yaman Umuroglu ,  Michaela Blott

    IPC: G06N3/08 ,  G06N3/04

    CPC classification number: G06N3/08 ,  G06N3/04 ,  G06N3/063 ,  H03K19/17732

    Abstract: In an example, a circuit of a neural network implemented in an integrated circuit (IC) includes a layer of hardware neurons, the layer including a plurality of inputs, a plurality of outputs, a plurality of weights, and a plurality of threshold values, each of the hardware neurons including: a logic circuit having inputs that receive first logic signals from at least a portion of the plurality of inputs and outputs that supply second logic signals corresponding to an exclusive NOR (XNOR) of the first logic signals and at least a portion of the plurality of weights; a counter circuit having inputs that receive the second logic signals and an output that supplies a count signal indicative of the number of the second logic signals having a predefined logic state; and a compare circuit having an input that receives the count signal and an output that supplies a logic signal having a logic state indicative of a comparison between the count signal and a threshold value of the plurality of threshold values; wherein the logic signal output by the compare circuit of each of the hardware neurons is provided as a respective one of the plurality of outputs.

    HETEROGENEOUS BALL PATTERN PACKAGE
    333.
    发明申请
    HETEROGENEOUS BALL PATTERN PACKAGE 审中-公开

    公开(公告)号：US20180033753A1

    公开(公告)日：2018-02-01

    申请号：US15225550

    申请日：2016-08-01

    Applicant: Xilinx, Inc.

    Inventor： Rafael C. Camarota

    IPC: H01L23/00 ,  H01L23/498

    CPC classification number: H01L24/09 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5286 ,  H01L24/17 ,  H01L24/83 ,  H01L2224/0903 ,  H01L2224/0912 ,  H01L2224/1712

    Abstract: Methods and apparatus are described for strategically arranging conductive elements (e.g., solder balls) of an integrated circuit (IC) package (and the corresponding conductive pads of a circuit board for electrical connection with the IC package) using a plurality of different pitches. One example integrated circuit (IC) package generally includes an integrated circuit die and an arrangement of electrically conductive elements coupled to the integrated circuit die. In at least one region of the arrangement, the conductive elements are disposed with a first pitch in a first dimension of the arrangement and with a second pitch in a second dimension of the arrangement, and the second pitch is different from the first pitch. The pitch of a given region may be based on mechanical, PCB routing, and/or signal integrity considerations.

    Rotated integrated circuit die and chip packages having the same
    334.
    发明授权
    Rotated integrated circuit die and chip packages having the same 有权

    公开(公告)号：US09882562B1

    公开(公告)日：2018-01-30

    申请号：US15371472

    申请日：2016-12-07

    Applicant: Xilinx, Inc.

    Inventor： Martin L. Voogel ,  Rafael C. Camarota ,  Henri Fraisse

    IPC: H03K19/177 ,  H03K19/00 ,  H01L23/498

    CPC classification number: H03K19/0008 ,  H01L23/49811 ,  H01L23/49838 ,  H03K19/17728 ,  H03K19/17744

    Abstract: An integrated circuit (IC) die and integrated circuit (IC) chip packages having such dies are described that leverage the symmetry of the arrangement of micro-bumps to advantageously reduce interposer cost and size requirements. In one example, an integrated circuit (IC) die is provided. The IC die includes a die body, a plurality of programmable tiles disposed in the die body, and a plurality of micro-bumps disposed in the die body. The die body includes a front face connecting a bottom exterior surface and a top exterior surface. A centerline of the die body is perpendicular to the front face and bifurcates the top exterior surface. At least two of the programmable tiles are of a common type. The micro-bumps adjacent the front face and coupled to the common type of programmable tiles have a substantially symmetrical orientation relative to a symmetry axis. The symmetry axis being one of (a) collinear with the centerline of the die body, or (b) parallel to the centerline of the die body.

    System and method for downlink processing in communication systems
    335.
    发明授权
    System and method for downlink processing in communication systems 有权

    公开(公告)号：US09876657B1

    公开(公告)日：2018-01-23

    申请号：US15451209

    申请日：2017-03-06

    Applicant: Xilinx, Inc.

    Inventor： Charles Jeon ,  Christoph E. Studer ,  Michael Wu ,  Christopher H. Dick

    IPC: H04K1/02 ,  H04L25/03 ,  H04L25/49 ,  H04B7/0452

    CPC classification number: H04L25/03159 ,  H04B7/0452 ,  H04L25/03012 ,  H04L2025/03426

    Abstract: An integrated circuit (IC) includes a downlink unit including an input to receive a first plurality of frequency domain (FD) symbols associated with data symbols for a plurality of users, and an iteration unit to perform a plurality of iterations based on adjustment values. Each iteration includes generating a second plurality of FD symbols by performing a precoding process based on the first plurality of FD symbols, generating a third plurality of time domain (TD) symbols by performing a first modulation process based on the second plurality of FD symbols, generating a fourth plurality of TD symbols by performing a dynamic range reduction process based on absolute values of the third plurality of TD symbols, and updating the adjustment values. The downlink unit further includes a decision unit configured to generate transmit TD symbols for transmission through a channel to the plurality of users.

    Voting circuit and self-correcting latches
    336.
    发明授权
    Voting circuit and self-correcting latches 有权

    公开(公告)号：US09871520B1

    公开(公告)日：2018-01-16

    申请号：US15237439

    申请日：2016-08-15

    Applicant: Xilinx, Inc.

    Inventor： Chi M. Nguyen ,  Robert I. Fu

    IPC: H03K19/003 ,  H03K19/177 ,  H03K3/356

    CPC classification number: H03K19/00392 ,  H03K3/356104 ,  H03K19/17764 ,  H03K19/23

    Abstract: The disclosed voting circuit includes a pull-up circuit connected to an output node and to a positive supply voltage. A pull-down circuit is connected to the output node and to ground, and the output node is coupled to receive true output of a first bi-stable circuit. The pull-up circuit pulls the output node to the positive supply voltage in response to complementary output signals from second and third bi-stable circuits being in a first state, and the pull-down circuit pulls the output node to ground in response to complementary output signals from second and third bi-stable circuits being in a second state that is opposite the first state.

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