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341.发明申请公开(公告)号：US20160124445A1
公开(公告)日：2016-05-05
申请号：US14530448
申请日：2014-10-31
Applicant: STMicroelectronics International N.V.
Inventor： Rajeev Jain , Chandrajit Debnath
IPC: G05F1/46
Abstract: A bandgap voltage generator includes a plurality of calibration transistors. A test circuit measures the bandgap reference voltage generated by the bandgap voltage generator and enables a subset of the calibration transistors to correct to the bandgap reference voltage.
Abstract translation: 带隙电压发生器包括多个校准晶体管。 测试电路测量由带隙电压发生器产生的带隙参考电压，并使得校准晶体管的子集能够校正到带隙参考电压。
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342.发明授权Automatic power switching and power harvesting in thin oxide open drain transmitter circuits, systems, and methods 有权薄氧化物开漏发射器电路，系统和方法中的自动功率开关和功率采集公开(公告)号：US09331671B2
公开(公告)日：2016-05-03
申请号：US14283043
申请日：2014-05-20
Applicant: STMICROELECTRONICS INTERNATIONAL N.V.
Inventor： Nitin Gupta , Paramjeet Singh Sahni , Tapas Nandy , Manish Garg
CPC classification number: H03K3/01 , H03K19/018528 , H04N5/44 , H04N5/63
Abstract: A power harvesting circuit includes a new transmitter topology that ensures that no junction of thin oxide transistors forming the power harvesting circuit will experience a voltage across junctions of the transistors that is more than a maximum tolerable junction voltage. A supplemental power feed circuit operates to provide a supplemental feed current to components in a transmitter circuit when power harvested from a receiver circuit is insufficient to adequately power these components of the transmitter circuit, which may occur during high frequency operation of communications channels coupling the transmitter and receiver circuits. The supplemental power feed circuit also operates to sink a shunt current when power harvested from the receiver circuit is more than is needed to power the components in the transmitter circuit.
Abstract translation: 功率收集电路包括新的发射机拓扑结构，其确保形成功率收集电路的薄氧化物晶体管的结不会经受超过最大可容忍结电压的晶体管结的电压。 补充供电电路用于在从接收器电路收集的功率不足以对发射机电路的这些组件充分供电时，向发射机电路中的组件提供补充馈电电流，这可能在耦合发射机的通信信道的高频操作期间发生 和接收器电路。 当从接收器电路收集的功率大于为发射机电路中的组件供电所需的功率时，辅助馈电电路还用于吸收分流电流。
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343.发明授权Phase locked loop (PLL) circuit with compensated bandwidth across process, voltage and temperature 有权锁相环（PLL）电路，具有过程，电压和温度的补偿带宽公开(公告)号：US09325324B1
公开(公告)日：2016-04-26
申请号：US14573002
申请日：2014-12-17
Applicant: STMicroelectronics International N.V.
Inventor： Nitin Gupta , Anand Kumar , Abhirup Lahiri
CPC classification number: H03L7/099 , H03L1/00 , H03L7/0895 , H03L7/0898 , H03L7/0995 , H03L7/1072 , H03L7/113 , H03L7/18
Abstract: A phase locked loop (PLL) circuit includes a phase comparison circuit configured to compare phase of an input signal to phase of a feedback signal and generate a control signal responsive to the phase comparison and an oscillator circuit configured to generate an output signal at a frequency set by said control signal, where said feedback signal is derived from said output signal. The PLL circuit further operates in a calibration mode of operation wherein the oscillator circuit operates in a frequency locked loop mode to compare frequency of the input signal to frequency of the output signal and center a gain of the oscillator circuit across process, voltage and temperature in response to the frequency comparison. Furthermore, bias current for a charge pump within the phase comparison circuit is calibrated during calibration mode of operation to match a temperature independent reference current.
Abstract translation: 锁相环（PLL）电路包括相位比较电路，其被配置为将输入信号的相位与反馈信号的相位进行比较，并响应于相位比较产生控制信号，以及振荡器电路，被配置为产生频率的输出信号 由所述控制信号设置，其中所述反馈信号从所述输出信号导出。 PLL电路进一步在校准操作模式下工作，其中振荡器电路以频率锁定环路模式操作，以将输入信号的频率与输出信号的频率进行比较，并将振荡器电路的增益集中在过程，电压和温度之间 响应频率比较。 此外，相位比较电路内的电荷泵的偏置电流在校准操作模式下进行校准，以匹配与温度无关的参考电流。
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344.发明授权CMOS oscillator having stable frequency with process, temperature, and voltage variation 有权具有稳定频率的CMOS振荡器，具有过程，温度和电压变化公开(公告)号：US09325323B2
公开(公告)日：2016-04-26
申请号：US14474091
申请日：2014-08-30
Applicant: STMICROELECTRONICS INTERNATIONAL N.V.
Inventor： Vikas Rana , Ganesh Raj R
CPC classification number: H03L1/00 , H03K3/011 , H03K3/0315 , H03K3/0322 , H03K3/354 , H03L1/022 , H03L7/0812 , H03L7/0891 , H03L7/0895 , H03L7/093 , H03L7/0995 , H03L7/0997 , H03L7/148 , H03L7/18
Abstract: A clock signal generation circuit configured to generate the clock signal having a frequency that is maintained across variations in a number of operating conditions, such as changes in supply voltage, temperature and processing time. In an embodiment, the frequency spread of the generated clock signal of a PVT-compensated CMOS ring oscillator is configured to compensate for variations in the supply voltage, as well as for variations in process and temperature via a process and temperature compensation circuit. The PVT-compensated CMOS ring oscillator includes a regulated voltage supply circuit to generate a supply voltage that is resistant to variations due to changes in the overall supply voltage.
Abstract translation: 时钟信号生成电路，被配置为生成具有在诸如电源电压，温度和处理时间的变化的操作条件的数量的变化中保持的频率的时钟信号。 在一个实施例中，PVT补偿的CMOS环形振荡器的所产生的时钟信号的频率扩展被配置为补偿电源电压的变化，以及通过处理和温度补偿电路对工艺和温度的变化。 PVT补偿的CMOS环形振荡器包括一个稳压电源，用于产生一个电源电压，该电源电压抵抗由于整个电源电压的变化引起的变化。
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公开(公告)号：US09319341B2
公开(公告)日：2016-04-19
申请号：US14059412
申请日：2013-10-21
Applicant: STMICROELECTRONICS INTERNATIONAL N.V.
Inventor： Pierre Muller , Samuel Dubouloz
IPC: H04L12/863 , H04L12/841 , H04L12/879
CPC classification number: H04L47/6245 , H04L47/28 , H04L49/901
Abstract: A plurality of frames of data are transmitted over a serial interface in a manner that limits interference on the interface. This involves generating a pseudo-random number and asserting a read control signal at a moment in time, wherein a timing of the moment in time is influenced by the pseudo-random number. In response to the asserted read control signal, a frame of data is read from a data buffer. The read frame of data is then transmitted over the serial interface. A number of alternative embodiments are possible, such as embodiments in which buffer read operations are triggered based on the buffer fill level, and other embodiments in which buffer read operations are triggered by a timer. By using the pseudo-random number to influence the buffer read operations, timing coherency between the reading of frames is made low, thereby limiting interference.
Abstract translation: 通过串行接口以限制对接口的干扰的方式发送多个数据帧。 这涉及在时刻产生伪随机数并断言读控制信号，其中时刻的定时受到伪随机数的影响。 响应于断言的读取控制信号，从数据缓冲器读取一帧数据。 然后通过串行接口传输读取的数据帧。 一些替代实施例是可能的，例如基于缓冲器填充级别触发缓冲器读取操作的实施例，以及其中缓冲器读取操作由定时器触发的其他实施例。 通过使用伪随机数来影响缓冲器读取操作，使得读取帧之间的定时一致性变低，从而限制干扰。
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Patent Agency Ranking
346.发明申请公开(公告)号：US20160103458A1
公开(公告)日：2016-04-14
申请号：US14512564
申请日：2014-10-13
Applicant: STMicroelectronics International N.V.
Inventor： Hemant Shukla , Saurabh Kumar Singh , Nitin Bansal
Abstract: An electronic device includes a power supply, a ground, and an intermediate ground having a voltage less than a voltage of the power supply and greater than a voltage of the ground. The electronic device also includes an error amplifier having an input stage coupled between the power supply and the ground, and an output stage coupled between the power supply and the intermediate ground. A ballast transistor is coupled to receive an output from the error amplifier. A feedback circuit is coupled to an output of the ballast transistor to generate feedback signals, and the error amplifier operates in response to the feedback signals.
Abstract translation: 电子设备包括电源，接地和具有小于电源电压的电压并且大于地的电压的中间接地。 电子设备还包括误差放大器，其具有耦合在电源和地之间的输入级，以及耦合在电源和中间接地之间的输出级。 耦合镇流器晶体管以接收来自误差放大器的输出。 反馈电路耦合到镇流器晶体管的输出以产生反馈信号，误差放大器响应于反馈信号而工作。
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347.发明授权Method for discovering a plurality of NFC-B devices by a NFC-B reader and corresponding NFC-B reader 有权用于通过NFC-B读取器和对应的NFC-B读取器发现多个NFC-B设备的方法公开(公告)号：US09313713B2
公开(公告)日：2016-04-12
申请号：US14706079
申请日：2015-05-07
Inventor： Jafer Hussain
CPC classification number: H04W40/246 , G06K7/10029 , H04B5/0031 , H04B5/0056 , H04W4/80 , H04W8/005 , H04W52/0216 , H04W74/085 , H04W84/18 , Y02D70/166 , Y02D70/42
Abstract: A discovered NFC-B listen mode device is put to SLEEP state only when there are one or more NFC-B listen mode devices yet to be discovered. An optimal value for the number of time slots indicated in a command is computed based on a combination of whether an empty time slot was detected and/or collision was detected and/or an NFC-B listen mode device was discovered in a discovery cycle. The compliance with the NFC Forum Activity Specification allows the direct activation of an NFC-B listen mode device, and thus speeds up the data transfer phase and consumes much less power.
Abstract translation: 只有当有一个或多个NFC-B监听模式设备尚未被发现时，才发现NFC-B监听模式设备处于休眠状态。 基于检测到空时隙和/或检测到冲突和/或在发现周期中是否发现NFC-B监听模式设备的组合来计算命令中指示的时隙数量的最佳值。 符合NFC论坛活动规范允许直接激活NFC-B聆听模式设备，从而加速数据传输阶段，并消耗更少的功耗。
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348.发明授权Pseudo dual port memory using a dual port cell and a single port cell with associated valid data bits and related methods 有权伪双端口内存使用双端口单元和单端口单元与相关的有效数据位和相关方法公开(公告)号：US09311990B1
公开(公告)日：2016-04-12
申请号：US14573106
申请日：2014-12-17
Applicant: STMicroelectronics International N.V.
Inventor： Harsh Rawat , Piyush Jain
IPC: G11C11/40 , G11C11/419 , G11C11/418
CPC classification number: G11C11/419 , G11C7/1045 , G11C7/1075 , G11C8/16 , G11C11/418
Abstract: A pseudo dual port memory includes a set of dual port memory cells having a read port and a write port, and configured to store data words in each of a plurality of addressed locations, and a set of single port memory cells having a read/write port, and configured to store data words in each of a plurality of addressed locations. A valid data storage unit is configured to store valid bits corresponding to the addressed locations of the set of dual port memory cells and the set of single port memory cells. Control circuitry is configured to access the addressed locations of the set of dual port memory cells and the set of single port memory cells. The control circuitry performs a simultaneous write operation using the write port of the set of dual port memory cells and the read/write port of the set of single port memory cells, and updates corresponding valid bits in the valid data storage unit, and performs a parallel read operation, at a same addressed location of the set of dual port memory cells and the set of single port memory cells, using the read port of the set of dual port memory cells and the read/write port of the set of single port memory cells, and determining which stored data word is valid based upon the corresponding valid bits in the valid data storage unit.
Abstract translation: 伪双端口存储器包括具有读端口和写端口的一组双端口存储器单元，并且被配置为在多个寻址位置的每一个中存储数据字，以及一组具有读/写的单端口存储器单元 并且被配置为将数据字存储在多个寻址位置的每一个中。 有效数据存储单元被配置为存储对应于该组双端口存储器单元和该组单端口存储器单元的寻址位置的有效位。 控制电路被配置为访问该组双端口存储器单元和一组单端口存储器单元的寻址位置。 控制电路使用该组双端口存储单元的写入端口和一组单端口存储器单元的读/写端口执行同时写入操作，并更新有效数据存储单元中的对应的有效位，并且执行 在双端口存储单元集合和单端口存储单元集合的相同寻址位置处使用双端口存储单元组的读端口和单端口集合的读/写端口进行并行读操作 并且基于有效数据存储单元中的相应的有效位来确定哪个存储的数据字是有效的。
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349.发明授权Active passive near field communication anti-collision method, initiator and tag 有权主动被动近场通信防碰撞方法，启动器和标签公开(公告)号：US09306627B2
公开(公告)日：2016-04-05
申请号：US14330505
申请日：2014-07-14
Applicant: STMicroelectronics International N.V.
Inventor： Achraf Dhayni
CPC classification number: H04B5/0025 , H04W74/06
Abstract: In near field communication between an active initiator and a plurality of passive listening devices, the initiator device obtains a unique identity code from each listening device using an initialization process. The initiator transmits a poll request signal including a sequence of coupled data including an identification vector and an allocation vector. Each listening device stores an embedded introduction vector. In response to receive of the poll request signal, the listening device compares each received introduction vector with its stored embedded introduction vector. If a match is found, the listening device calculates a time slot for transmission of its poll response signal based on the coupled allocation vector with the matched introduction vector. The time slot calculated will not overlap with any other time slot so that bit level collisions in the poll response signals will be avoided.
Abstract translation: 在主动启动器和多个被动收听装置之间的近场通信中，发起者设备使用初始化过程从每个监听装置获得唯一的身份码。 启动器发送包括包括识别向量和分配向量的耦合数据序列的轮询请求信号。 每个听音装置存储嵌入的引入向量。 响应于轮询请求信号的接收，收听装置将每个接收到的引入向量与其存储的嵌入式引入向量进行比较。 如果发现匹配，则听音装置基于具有匹配引入向量的耦合分配向量来计算用于发送其轮询响应信号的时隙。 计算的时隙不会与任何其他时隙重叠，以便避免轮询响应信号中的位级别冲突。
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350.发明申请Method for Managing the Operation of an Object that is Able to Contactlessly Communicate with a Reader 审中-公开用于管理能够与读取器非接触地通信的对象的操作的方法公开(公告)号：US20160092762A1
公开(公告)日：2016-03-31
申请号：US14839673
申请日：2015-08-28
Applicant: STMicroelectronics International N.V.
Inventor： Achraf Dhayni
IPC: G06K19/07 , H03C1/08 , G06K19/073
CPC classification number: G06K19/0726 , G06K7/0095 , G06K19/0722 , G06K19/073 , H03C1/08 , H04B5/0031 , H04B5/0075
Abstract: A method for managing the operation of an object capable of contactless communication with a reader magnetically coupled to the object includes a phase for transmission of information from the object to the reader and includes a modulation of the impedance of a load connected across the terminals of the antenna of the object. Prior to the transmission phase, a monitoring phase includes a monitoring of the level of amplitude modulation of a modulated test signal present at the antenna of the object and resulting from a test modulation of the impedance of the load and a capacitive modification of the impedance of the load if this level is lower than a threshold.
Abstract translation: 用于管理能够与磁性耦合到对象的读取器进行非接触通信的对象的操作的方法包括用于从对象向读取器传输信息的阶段，并且包括对连接到对象的终端的负载的阻抗的调制 物体的天线。 在传输阶段之前，监测阶段包括监测存在于物体的天线上的调制测试信号的幅度调制水平，并且由对负载的阻抗的测试调制产生的， 该级别低于阈值时的负载。
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