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    Contact structure for semiconductor devices and corresponding manufacturing process
    341.
    发明申请
    Contact structure for semiconductor devices and corresponding manufacturing process 有权
    半导体器件的接触结构及相应的制造工艺

    公开(公告)号：US20020050627A1

    公开(公告)日：2002-05-02

    申请号：US10033508

    申请日：2001-12-28

    Applicant: STMicroelectronics S.r.I.

    Inventor： Raffaele Zambrano

    IPC: H01L029/00

    CPC classification number: H01L27/11502 ,  H01L21/76801 ,  H01L21/76837 ,  H01L21/76877 ,  H01L27/0629 ,  H01L27/1085 ,  H01L28/55 ,  H01L28/60 ,  H01L28/75

    Abstract: A contact structure for semiconductor devices which are integrated on a semiconductor layer is provided. The structure comprises at least one MOS device and at least one capacitor element where the contact is provided at an opening formed in an insulating layer which overlies at least in part the semiconductor layer. Further, the opening has its surface edges, walls and bottom coated with a metal layer and filled with an insulating layer.

    Abstract translation: 提供集成在半导体层上的用于半导体器件的接触结构。 该结构包括至少一个MOS器件和至少一个电容器元件，其中触点设置在形成在至少部分半导体层的绝缘层中的开口处。 此外，开口具有其表面边缘，壁和底部涂覆有金属层并且填充有绝缘层。

    Processor having internal control instructions
    343.
    发明申请
    Processor having internal control instructions 有权
    具有内部控制指令的处理器

    公开(公告)号：US20020035679A1

    公开(公告)日：2002-03-21

    申请号：US09998568

    申请日：2001-11-16

    Applicant: STMicroelectronics S.r.I.

    Inventor： Francesco Pappalardo ,  Davide Tesi ,  Francesco Nino Mammoliti ,  Francesco Bombaci

    IPC: G06F009/00

    CPC classification number: G06F9/30181 ,  G06F9/30003 ,  G06F9/30145

    Abstract: A processor is provided with a set of instructions formed, in general, of an operation section and an operand section. For at least one of the instructions, the operand section represents operation control signals of the processor. In this way, an extension of the set of instructions can be achieved for tailoring the set of instructions to the user's own requirements. Consequently, the processor control unit should be capable of coupling its outputs to its inputs upon receiving one such instruction, thereby to transfer such internal operation control signals without interpretation.

    Abstract translation: 处理器设置有一组通常由操作部分和操作数部分形成的指令。 对于至少一个指令，操作数部分表示处理器的操作控制信号。 以这种方式，可以实现该组指令的扩展，以便根据用户自己的要求定制指令集。 因此，处理器控制单元应该能够在接收到一个这样的指令时将其输出耦合到其输入，从而在没有解释的情况下传送这样的内部操作控制信号。

    Fully digital control and drive combination IC with on-board DSP for disk mass storage device
    344.
    发明申请
    Fully digital control and drive combination IC with on-board DSP for disk mass storage device 有权
    全数字控制和驱动组合IC与板载大容量存储设备的板载DSP

    公开(公告)号：US20020001153A1

    公开(公告)日：2002-01-03

    申请号：US09812715

    申请日：2001-03-20

    Applicant: STMicroelectronics S.r.I.

    Inventor： Giuseppe Maiocchi

    IPC: G11B015/46

    CPC classification number: G11B19/20 ,  G11B19/28 ,  G11B21/02

    Abstract: The device is for driving and controlling a rotation motor and a voice coil motor for a hard disk drive system that includes a disk and an arm carrying a read/write head to be positioned with respect thereto. A duty-cycle control loop including a current sensing circuit is connected to the voice coil motor, and an arm position control loop including a speed detection circuit is also connected to the voice coil motor. The duty-cycle control loop and the arm position control loop are digitally implemented by a DSP as a function of digital data representing a first analog signal generated by the current sensing circuit representative of current conducting in a winding of the voice coil motor, and a second analog signal generated by the speed detection circuit representative of an instant speed of the voice coil motor.

    Abstract translation: 该装置用于驱动和控制用于硬盘驱动系统的旋转电动机和音圈电动机，该系统包括盘和携带读/写头相对于其定位的臂。 包括电流感测电路的占空比控制回路连接到音圈电动机，并且包括速度检测电路的臂位置控制回路也连接到音圈电动机。 占空比控制回路和臂位置控制回路由DSP作为数字数据数字地实现，该数字数据表示由代表在线圈电动机的绕组中的电流传导的电流感测电路产生的第一模拟信号，以及 由速度检测电路产生的代表音圈电机瞬时速度的第二模拟信号。

    Row selection circuit for fast memory devices
    345.
    发明申请
    Row selection circuit for fast memory devices 有权
    用于快速存储器件的行选择电路

    公开(公告)号：US20010024131A1

    公开(公告)日：2001-09-27

    申请号：US09745286

    申请日：2000-12-21

    Applicant: STMicroelectronics S.r.I

    Inventor： Raffaele Solimene

    IPC: H03K005/19

    CPC classification number: G11C8/08 ,  G11C8/10 ,  G11C16/08 ,  G11C16/32

    Abstract: The selection/deselection circuit is for non-volatile memory word lines having a decoding line connected between a supply voltage and ground, and including a series of decoding transistors of the same conductivity controlled by respective selection signals and at least a load transistor whose conductivity is opposite to the conductivity of the decoding transistors in series with the series of transistors and biased by a control voltage. The load transistor produces an activating or deactivating voltage of a memory word line, and a circuit for controlling the load transistor is provided. Such an auxiliary control circuit includes a sensing element in series with the decoding transistors and the load transistor for producing a sensing signal switching between a first value when only one memory line is actually selected and a second value when multiple memory word lines appear to be simultaneously selected. Also, an inverter receives the sensing signal and outputs a first signal. A high pass filter receives the first signal and produces a control transient voltage for transitorily bringing the load transistor to a state of full conduction when the sensing signal switches from the first value to the second value.

    Abstract translation: 选择/取消选择电路是用于具有连接在电源电压和地之间的解码线的非易失性存储字线，并且包括由各个选择信号控制的相同电导率的一系列解码晶体管和至少一个负载晶体管，其导电性为 与与晶体管系列串联的解码晶体管的导电性相反，并由控制电压偏置。 负载晶体管产生存储字线的激活或去激活电压，并且提供用于控制负载晶体管的电路。 这样的辅助控制电路包括与解码晶体管和负载晶体管串联的感测元件，用于当仅实际选择一个存储器线路时产生在第一值之间切换的感测信号，并且当多个存储器字线似乎同时显示时的第二值 选择。 此外，逆变器接收感测信号并输出​​第一信号。 当检测信号从第一值切换到第二值时，高通滤波器接收第一信号并产生控制瞬态电压，用于将负载晶体管暂时地导通到全导通状态。

    Process for manufacturing non-volatile memory cells integrated on a semiconductor substrate
    346.
    发明申请
    Process for manufacturing non-volatile memory cells integrated on a semiconductor substrate 有权
    用于制造集成在半导体衬底上的非易失性存储单元的工艺

    公开(公告)号：US20010016379A1

    公开(公告)日：2001-08-23

    申请号：US09750449

    申请日：2000-12-28

    Applicant: STMicroelectronics S.r.I.

    Inventor： Nicola Nastasi ,  Dorotea Arcidiacono ,  Stefano Mazzali

    IPC: H01L021/8238

    CPC classification number: H01L27/11521

    Abstract: A method is provided for manufacturing electronic non-volatile memory devices on a semiconductor substrate including a matrix of memory cells having floating gate regions formed on respective active areas and an oxide layer separating the active areas. The method may include forming sidewalls of the floating gate regions that are slanted with respect to a surface of the semiconductor substrate, forming a trench in the oxide layer following the formation of the floating gate regions, and forming a plug of polycrystalline silicon in the trench. The slanted sidewalls of the floating gate regions provide a lead-in for the formation of upper layers.

    Abstract translation: 提供了一种用于在半导体衬底上制造电子非易失性存储器件的方法，该半导体衬底包括具有形成在各自的有源区上的浮动栅极区域和分离有源区域的氧化物层的存储器单元的矩阵。 该方法可以包括形成相对于半导体衬底的表面倾斜的浮动栅极区域的侧壁，在形成浮动栅极区域之后在氧化物层中形成沟槽，以及在沟槽中形成多晶硅插塞 。 浮动栅极区域的倾斜侧壁提供用于形成上层的引入。

    REVERSE BATTERY PROTECTION CIRCUIT
    349.
    发明公开
    REVERSE BATTERY PROTECTION CIRCUIT 审中-公开

    公开(公告)号：US20230411953A1

    公开(公告)日：2023-12-21

    申请号：US17844306

    申请日：2022-06-20

    Applicant: STMicroelectronics (China) Investment Co., Ltd. ,  STMicroelectronics S.r.I.

    Inventor： Ping Chen ,  Hui Yan ,  Vincenzo Randazzo ,  Alberto Marzo ,  Andrea Camillo Re

    IPC: H02H7/18 ,  H02H1/00

    CPC classification number: H02H7/18 ,  H02H1/0007

    Abstract: A circuit for reverse battery protection includes an isolation circuit and a control circuit. The isolation is circuit coupled between a gate output of an electronic fuse (E-fuse) and at least one external metal-oxide-semiconductor field-effect transistor (MOSFET). The E-fuse is coupled between a battery voltage pin and an external ground pin and further coupled to a microcontroller. The isolation circuit is configured to disconnect the gate output from the at least one external MOSFET when the battery is installed with reverse polarity. The control circuit is coupled between the external ground pin and the at least one external MOSFET. The control circuit is configured to turn on the at least one external MOSFET when the battery is installed with the reverse polarity.

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