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    METHOD AND SYSTEM TO AUTOMATICALLY CORRECT PROJECTED IMAGE DEFECTS
    351.
    发明申请
    METHOD AND SYSTEM TO AUTOMATICALLY CORRECT PROJECTED IMAGE DEFECTS 有权
    自动校正投影图像缺陷的方法和系统

    公开(公告)号：US20090147346A1

    公开(公告)日：2009-06-11

    申请号：US12366929

    申请日：2009-02-06

    Applicant: FRANK BRYANT

    Inventor： FRANK BRYANT

    IPC: G02B26/02

    CPC classification number: G02B26/0833

    Abstract: An apparatus is provided that includes a light source, an array of light-reflecting devices, and a processor for positioning the light-reflecting devices so as to display an image on the display screen. Each of the light-reflecting devices selectively reflects the light from the light source onto a corresponding pixel of a display screen. The processor positions a first of the light-reflecting devices such that light from the light source is reflected by the first light-reflecting device onto a first pixel of the display screen, which is different than the pixel of the display screen that corresponds to the first light-reflecting device. A similar apparatus is also provided in which the processor instead positions the first light-reflecting device such that light from the light source is reflected by the first light-reflecting device onto a first area of the display screen, which is located between the pixels of the display screen that correspond to the first light-reflecting device and an adjacent second light-reflecting device.

    Abstract translation: 提供了一种装置，其包括光源，光反射装置阵列和用于定位光反射装置以便在显示屏上显示图像的处理器。 每个光反射装置选择性地将来自光源的光反射到显示屏的相应像素上。 处理器将第一个光反射装置定位成使得来自光源的光被第一光反射装置反射到显示屏的第一像素上，该第一像素不同于对应于显示屏的显示屏的像素 第一光反射装置。 还提供了一种类似的装置，其中处理器替代地定位第一光反射装置，使得来自光源的光被第一光反射装置反射到位于显示屏的第一区域之间，该第一区域位于 对应于第一光反射装置的显示屏和相邻的第二光反射装置。

    Receiver for performing adaptive equalization and method
    353.
    发明授权
    Receiver for performing adaptive equalization and method 有权
    用于执行自适应均衡和方法的接收机

    公开(公告)号：US07539244B2

    公开(公告)日：2009-05-26

    申请号：US10953710

    申请日：2004-09-29

    Applicant: Krishna B. Thirunagari ,  Giorgio Mariani

    Inventor： Krishna B. Thirunagari ,  Giorgio Mariani

    IPC: H03H7/30 ,  H03H7/40 ,  H03K5/159 ,  H03K9/00 ,  H04B14/06

    CPC classification number: H04L25/03159 ,  H04L2025/03522

    Abstract: A receiver includes a filter capable of receiving an input signal and generating an output signal. The filter provides a transfer function. The filter includes a first stage capable of adjusting a pole and a first zero of the transfer function. The filter also includes a second stage capable of adjusting a second zero of the transfer function. In addition, the filter includes a third stage capable of adjusting a third zero of the transfer function.

    Abstract translation: 接收机包括能够接收输入信号并产生输出信号的滤波器。 滤波器提供传递函数。 滤波器包括能够调节极点和传递函数的第一零点的第一级。 滤波器还包括能够调整传递函数的第二零点的第二级。 此外，滤波器包括能够调整传递函数的第三个零的第三级。

    Hyperprocessor
    354.
    发明授权
    Hyperprocessor 有权
    超处理器

    公开(公告)号：US07533382B2

    公开(公告)日：2009-05-12

    申请号：US10283653

    申请日：2002-10-30

    Applicant: Faraydon O. Karim

    Inventor： Faraydon O. Karim

    IPC: G06F9/46 ,  G06F15/00

    CPC classification number: G06F9/4843 ,  G06F9/30098 ,  G06F9/3851

    Abstract: A hyperprocessor includes a control processor controlling tasks executed by a plurality of processor cores, each of which may include multiple execution units, or special hardware units. The control processor schedules tasks according to control threads for the tasks created during compilation and comprising a hardware context including register files, a program counter and status bits for the respective task. The tasks are dispatched to the processor cores or special hardware units for parallel, sequential, out-of-order or speculative execution. A universal register file contains data to be operated on by the task, and an interconnect couples at least the processor cores or special hardware units to each other and to the universal register file, allowing each node to communicate with any other node.

    Abstract translation: 超处理器包括控制处理器，其控制由多个处理器核执行的任务，每个处理器核可以包括多个执行单元或特殊硬件单元。 控制处理器根据编译期间创建的任务的控制线程调度任务，并且包括包括寄存器文件的硬件上下文，程序计数器和相应任务的状态位。 将任务分派到处理器内核或特殊硬件单元进行并行，顺序，无序或推测执行。 通用寄存器文件包含要由任务操作的数据，并且互连至少将处理器核心或特殊硬件单元彼此耦合到通用寄存器文件，从而允许每个节点与任何其他节点通信。

    PROCESSOR SUPPORTING VECTOR MODE EXECUTION
    356.
    发明申请
    PROCESSOR SUPPORTING VECTOR MODE EXECUTION 有权
    处理器支持向量模式执行

    公开(公告)号：US20090106537A1

    公开(公告)日：2009-04-23

    申请号：US12341250

    申请日：2008-12-22

    Applicant: Osvaldo M. Colavin

    Inventor： Osvaldo M. Colavin

    IPC: G06F9/30

    CPC classification number: G06F9/325 ,  G06F9/30076 ,  G06F9/3013 ,  G06F9/30138 ,  G06F9/30189 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3853 ,  G06F9/3867 ,  G06F9/3887

    Abstract: An improved superscalar processor. The processor includes multiple lanes, allowing multiple instructions in a bundle to be executed in parallel. In vector mode, the parallel lanes may be used to execute multiple instances of a bundle, representing multiple iterations of the bundle in a vector run. Scheduling logic determines whether, for each bundle, multiple instances can be executed in parallel. If multiple instances can be executed in parallel, coupling circuitry couples an instance of the bundle from one lane into one or more other lanes. In each lane, register addresses are renamed to ensure proper execution of the bundles in the vector run. Additionally, the processor may include a register bank separate from the architectural register file. Renaming logic can generate addresses to this separate register bank that are longer than used to address architectural registers, allowing longer vectors and more efficient processor operation.

    Abstract translation: 改进的超标量处理器 处理器包括多个通道，允许并行执行捆绑中的多个指令。 在向量模式中，并行通道可用于执行捆绑的多个实例，表示向量运行中捆绑的多次迭代。 调度逻辑决定了对于每个bundle，是否可以并行执行多个实例。 如果并行执行多个实例，耦合电路将一个实体的捆绑从一个通道耦合到一个或多个其他通道。 在每个通道中，重命名寄存器地址以确保在向量运行中正确执行捆绑。 此外，处理器可以包括与架构寄存器文件分离的寄存器组。 重命名逻辑可以为这个单独的寄存器组生成比用于寻址架构寄存器更长的地址，允许更长的向量和更高效的处理器操作。

    ISOLATED VERTICAL POWER DEVICE STRUCTURE WITH BOTH N-DOPED AND P-DOPED TRENCHES
    357.
    发明申请
    ISOLATED VERTICAL POWER DEVICE STRUCTURE WITH BOTH N-DOPED AND P-DOPED TRENCHES 有权
    分离的垂直功率器件结构，具有两个N型和P型掺杂的TRINCHES

    公开(公告)号：US20090051001A1

    公开(公告)日：2009-02-26

    申请号：US12259834

    申请日：2008-10-28

    Applicant: Richard Austin Blanchard

    Inventor： Richard Austin Blanchard

    IPC: H01L27/02

    CPC classification number: H01L29/74 ,  H01L29/0634 ,  H01L29/0657 ,  H01L29/0692 ,  H01L29/0834 ,  H01L29/66363 ,  H01L29/87

    Abstract: A method for manufacturing an isolated vertical power device includes forming, in a back surface of a first conductivity type substrate, back isolation wall trenches that surround a conduction region of the device. In a front surface of the substrate, front isolation wall trenches are formed around the conduction region. Thereafter, a film containing a second type dopant is deposited in the front and back isolation wall trenches. In the conduction region on the back surface, conduction region trenches are formed inside the perimeter of the isolation wall trenches. A first type dopant is deposited in the conduction region trenches. The dopants are diffused from the conduction region trenches and isolation wall trenches to form a first conductivity type conduction region structure and a second conductivity type isolation wall.

    Abstract translation: 一种用于制造隔离垂直功率器件的方法包括在第一导电类型衬底的背表面中形成围绕器件的导电区域的后隔离壁沟槽。 在基板的前表面上，在导电区域周围形成前隔离壁沟槽。 此后，在前后隔离壁沟槽中沉积含有第二种掺杂剂的膜。 在背表面的导电区域中，导电区沟槽形成在隔离壁沟槽周边的内部。 第一种掺杂剂沉积在导电区沟槽中。 掺杂剂从导电区沟槽和隔离壁沟槽扩散以形成第一导电类型的导电区域结构和第二导电型隔离壁。

    Apparatus and method for reducing propagation delay in a conductor system selectable to carry a single signal or independent signals
    358.
    发明授权
    Apparatus and method for reducing propagation delay in a conductor system selectable to carry a single signal or independent signals 有权
    用于减少可选择承载单个信号或独立信号的导体系统中的传播延迟的装置和方法

    公开(公告)号：US07495526B2

    公开(公告)日：2009-02-24

    申请号：US10997089

    申请日：2004-11-23

    Applicant: James Brady ,  Duane Giles Laurent

    Inventor： James Brady ,  Duane Giles Laurent

    IPC: H01P1/10 ,  H01P3/08

    CPC classification number: H01L23/5225 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An apparatus and method is provided that reduces the propagation delay in a conductor carrying an electrical signal from a first area of a circuit to a second area of the circuit. The conductor is fabricated to include a first conductor extending from the first area to the second area. The conductor also includes a second conductor extending substantially parallel and along the first conductor and electrically connected to the first conductor. A third and additional conductors may also be used which extend substantially parallel and along the first conductor and are electrically connected to the first conductor. The additional second conductor (and any additional conductors) reduces the capacitance of the conductor thereby reducing the propagation delay in the conductor (increasing the speed of the signal). The additional conductor(s) effectively “shield” the first conductor from some capacitance that the first conductor would normally “see” without the use of such additional conductors.

    Abstract translation: 提供了一种装置和方法，其减少了将电信号从电路的第一区域传递到电路的第二区域的导体中的传播延迟。 导体被制造成包括从第一区域延伸到第二区域的第一导体。 导体还包括基本上平行且沿着第一导体延伸并电连接到第一导体的第二导体。 还可以使用第三和附加导体，其基本上平行延伸并且沿着第一导体延伸并且电连接到第一导体。 额外的第二导体（和任何附加导体）减小了导体的电容，从而减少了导体中的传播延迟（增加了信号的速度）。 附加导体有效地“屏蔽”第一导体不受第一导体通常“看到”的一些电容，而不使用这种附加导体。

    Instruction vector-mode processing in multi-lane processor by multiplex switch replicating instruction in one lane to select others along with updated operand address
    359.
    发明授权
    Instruction vector-mode processing in multi-lane processor by multiplex switch replicating instruction in one lane to select others along with updated operand address 有权
    在多通道处理器中通过多路复用开关复制指令在一条通道中进行指令矢量模式处理，以选择其他连同更新的操作数地址

    公开(公告)号：US07493475B2

    公开(公告)日：2009-02-17

    申请号：US11602277

    申请日：2006-11-15

    Applicant: Osvaldo M. Colavin

    Inventor： Osvaldo M. Colavin

    IPC: G06F9/30

    CPC classification number: G06F9/325 ,  G06F9/30076 ,  G06F9/3013 ,  G06F9/30138 ,  G06F9/30189 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3853 ,  G06F9/3867 ,  G06F9/3887

    Abstract: An improved superscalar processor. The processor includes multiple lanes, allowing multiple instructions in a bundle to be executed in parallel. In vector mode, the parallel lanes may be used to execute multiple instances of a bundle, representing multiple iterations of the bundle in a vector run. Scheduling logic determines whether, for each bundle, multiple instances can be executed in parallel. If multiple instances can be executed in parallel, coupling circuitry couples an instance of the bundle from one lane into one or more other lanes. In each lane, register addresses are renamed to ensure proper execution of the bundles in the vector run. Additionally, the processor may include a register bank separate from the architectural register file. Renaming logic can generate addresses to this separate register bank that are longer than used to address architectural registers, allowing longer vectors and more efficient processor operation.

    Abstract translation: 改进的超标量处理器 处理器包括多个通道，允许并行执行捆绑中的多个指令。 在向量模式中，并行通道可用于执行捆绑的多个实例，表示向量运行中捆绑的多次迭代。 调度逻辑决定了对于每个bundle，是否可以并行执行多个实例。 如果并行执行多个实例，耦合电路将一个实体的捆绑从一个通道耦合到一个或多个其他通道。 在每个通道中，重命名寄存器地址以确保在向量运行中正确执行捆绑。 此外，处理器可以包括与架构寄存器文件分离的寄存器组。 重命名逻辑可以为这个单独的寄存器组生成比用于寻址架构寄存器更长的地址，允许更长的向量和更高效的处理器操作。

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