公开(公告)号：US09319341B2

公开(公告)日：2016-04-19

申请号：US14059412

申请日：2013-10-21

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Pierre Muller ,  Samuel Dubouloz

IPC: H04L12/863 ,  H04L12/841 ,  H04L12/879

CPC classification number: H04L47/6245 ,  H04L47/28 ,  H04L49/901

Abstract: A plurality of frames of data are transmitted over a serial interface in a manner that limits interference on the interface. This involves generating a pseudo-random number and asserting a read control signal at a moment in time, wherein a timing of the moment in time is influenced by the pseudo-random number. In response to the asserted read control signal, a frame of data is read from a data buffer. The read frame of data is then transmitted over the serial interface. A number of alternative embodiments are possible, such as embodiments in which buffer read operations are triggered based on the buffer fill level, and other embodiments in which buffer read operations are triggered by a timer. By using the pseudo-random number to influence the buffer read operations, timing coherency between the reading of frames is made low, thereby limiting interference.

Abstract translation: 通过串行接口以限制对接口的干扰的方式发送多个数据帧。 这涉及在时刻产生伪随机数并断言读控制信号，其中时刻的定时受到伪随机数的影响。 响应于断言的读取控制信号，从数据缓冲器读取一帧数据。 然后通过串行接口传输读取的数据帧。 一些替代实施例是可能的，例如基于缓冲器填充级别触发缓冲器读取操作的实施例，以及其中缓冲器读取操作由定时器触发的其他实施例。 通过使用伪随机数来影响缓冲器读取操作，使得读取帧之间的定时一致性变低，从而限制干扰。

公开(公告)号：US20160103458A1

公开(公告)日：2016-04-14

申请号：US14512564

申请日：2014-10-13

Applicant: STMicroelectronics International N.V.

Inventor： Hemant Shukla ,  Saurabh Kumar Singh ,  Nitin Bansal

IPC: G05F1/46 ,  G05F1/575

CPC classification number: G05F1/468 ,  G05F1/575

Abstract: An electronic device includes a power supply, a ground, and an intermediate ground having a voltage less than a voltage of the power supply and greater than a voltage of the ground. The electronic device also includes an error amplifier having an input stage coupled between the power supply and the ground, and an output stage coupled between the power supply and the intermediate ground. A ballast transistor is coupled to receive an output from the error amplifier. A feedback circuit is coupled to an output of the ballast transistor to generate feedback signals, and the error amplifier operates in response to the feedback signals.

Abstract translation: 电子设备包括电源，接地和具有小于电源电压的电压并且大于地的电压的中间接地。 电子设备还包括误差放大器，其具有耦合在电源和地之间的输入级，以及耦合在电源和中间接地之间的输出级。 耦合镇流器晶体管以接收来自误差放大器的输出。 反馈电路耦合到镇流器晶体管的输出以产生反馈信号，误差放大器响应于反馈信号而工作。

公开(公告)号：US09313713B2

公开(公告)日：2016-04-12

申请号：US14706079

申请日：2015-05-07

Applicant: STMicroelectronics International N.V.—Netherlands

Inventor： Jafer Hussain

IPC: H04B5/00 ,  H04W40/24 ,  H04W52/02 ,  G06K7/10 ,  H04W74/08 ,  H04W8/00 ,  H04W4/00 ,  H04W84/18

CPC classification number: H04W40/246 ,  G06K7/10029 ,  H04B5/0031 ,  H04B5/0056 ,  H04W4/80 ,  H04W8/005 ,  H04W52/0216 ,  H04W74/085 ,  H04W84/18 ,  Y02D70/166 ,  Y02D70/42

Abstract: A discovered NFC-B listen mode device is put to SLEEP state only when there are one or more NFC-B listen mode devices yet to be discovered. An optimal value for the number of time slots indicated in a command is computed based on a combination of whether an empty time slot was detected and/or collision was detected and/or an NFC-B listen mode device was discovered in a discovery cycle. The compliance with the NFC Forum Activity Specification allows the direct activation of an NFC-B listen mode device, and thus speeds up the data transfer phase and consumes much less power.

Abstract translation: 只有当有一个或多个NFC-B监听模式设备尚未被发现时，才发现NFC-B监听模式设备处于休眠状态。 基于检测到空时隙和/或检测到冲突和/或在发现周期中是否发现NFC-B监听模式设备的组合来计算命令中指示的时隙数量的最佳值。 符合NFC论坛活动规范允许直接激活NFC-B聆听模式设备，从而加速数据传输阶段，并消耗更少的功耗。

公开(公告)号：US09311990B1

公开(公告)日：2016-04-12

申请号：US14573106

申请日：2014-12-17

Applicant: STMicroelectronics International N.V.

Inventor： Harsh Rawat ,  Piyush Jain

IPC: G11C11/40 ,  G11C11/419 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C7/1045 ,  G11C7/1075 ,  G11C8/16 ,  G11C11/418

Abstract: A pseudo dual port memory includes a set of dual port memory cells having a read port and a write port, and configured to store data words in each of a plurality of addressed locations, and a set of single port memory cells having a read/write port, and configured to store data words in each of a plurality of addressed locations. A valid data storage unit is configured to store valid bits corresponding to the addressed locations of the set of dual port memory cells and the set of single port memory cells. Control circuitry is configured to access the addressed locations of the set of dual port memory cells and the set of single port memory cells. The control circuitry performs a simultaneous write operation using the write port of the set of dual port memory cells and the read/write port of the set of single port memory cells, and updates corresponding valid bits in the valid data storage unit, and performs a parallel read operation, at a same addressed location of the set of dual port memory cells and the set of single port memory cells, using the read port of the set of dual port memory cells and the read/write port of the set of single port memory cells, and determining which stored data word is valid based upon the corresponding valid bits in the valid data storage unit.

Abstract translation: 伪双端口存储器包括具有读端口和写端口的一组双端口存储器单元，并且被配置为在多个寻址位置的每一个中存储数据字，以及一组具有读/写的单端口存储器单元 并且被配置为将数据字存储在多个寻址位置的每一个中。 有效数据存储单元被配置为存储对应于该组双端口存储器单元和该组单端口存储器单元的寻址位置的有效位。 控制电路被配置为访问该组双端口存储器单元和一组单端口存储器单元的寻址位置。 控制电路使用该组双端口存储单元的写入端口和一组单端口存储器单元的读/写端口执行同时写入操作，并更新有效数据存储单元中的对应的有效位，并且执行 在双端口存储单元集合和单端口存储单元集合的相同寻址位置处使用双端口存储单元组的读端口和单端口集合的读/写端口进行并行读操作 并且基于有效数据存储单元中的相应的有效位来确定哪个存储的数据字是有效的。

公开(公告)号：US09306627B2

公开(公告)日：2016-04-05

申请号：US14330505

申请日：2014-07-14

Applicant: STMicroelectronics International N.V.

Inventor： Achraf Dhayni

IPC: H04B5/00 ,  H04B7/00 ,  H04W74/06

CPC classification number: H04B5/0025 ,  H04W74/06

Abstract: In near field communication between an active initiator and a plurality of passive listening devices, the initiator device obtains a unique identity code from each listening device using an initialization process. The initiator transmits a poll request signal including a sequence of coupled data including an identification vector and an allocation vector. Each listening device stores an embedded introduction vector. In response to receive of the poll request signal, the listening device compares each received introduction vector with its stored embedded introduction vector. If a match is found, the listening device calculates a time slot for transmission of its poll response signal based on the coupled allocation vector with the matched introduction vector. The time slot calculated will not overlap with any other time slot so that bit level collisions in the poll response signals will be avoided.

Abstract translation: 在主动启动器和多个被动收听装置之间的近场通信中，发起者设备使用初始化过程从每个监听装置获得唯一的身份码。 启动器发送包括包括识别向量和分配向量的耦合数据序列的轮询请求信号。 每个听音装置存储嵌入的引入向量。 响应于轮询请求信号的接收，收听装置将每个接收到的引入向量与其存储的嵌入式引入向量进行比较。 如果发现匹配，则听音装置基于具有匹配引入向量的耦合分配向量来计算用于发送其轮询响应信号的时隙。 计算的时隙不会与任何其他时隙重叠，以便避免轮询响应信号中的位级别冲突。

公开(公告)号：US20160092762A1

公开(公告)日：2016-03-31

申请号：US14839673

申请日：2015-08-28

Applicant: STMicroelectronics International N.V.

Inventor： Achraf Dhayni

IPC: G06K19/07 ,  H03C1/08 ,  G06K19/073

CPC classification number: G06K19/0726 ,  G06K7/0095 ,  G06K19/0722 ,  G06K19/073 ,  H03C1/08 ,  H04B5/0031 ,  H04B5/0075

Abstract: A method for managing the operation of an object capable of contactless communication with a reader magnetically coupled to the object includes a phase for transmission of information from the object to the reader and includes a modulation of the impedance of a load connected across the terminals of the antenna of the object. Prior to the transmission phase, a monitoring phase includes a monitoring of the level of amplitude modulation of a modulated test signal present at the antenna of the object and resulting from a test modulation of the impedance of the load and a capacitive modification of the impedance of the load if this level is lower than a threshold.

Abstract translation: 用于管理能够与磁性耦合到对象的读取器进行非接触通信的对象的操作的方法包括用于从对象向读取器传输信息的阶段，并且包括对连接到对象的终端的负载的阻抗的调制 物体的天线。 在传输阶段之前，监测阶段包括监测存在于物体的天线上的调制测试信号的幅度调制水平，并且由对负载的阻抗的测试调制产生的， 该级别低于阈值时的负载。

公开(公告)号：US09276477B2

公开(公告)日：2016-03-01

申请号：US14085914

申请日：2013-11-21

Applicant: STMicroelectronics International N.V.

Inventor： Matthieu Thomas ,  Bohumil Janik ,  Ondrej Tlaskal

IPC: H02M3/157 ,  H02M3/158 ,  H02M1/00

CPC classification number: H02M3/158 ,  H02M3/1588 ,  H02M2001/0009 ,  H02M2001/0025 ,  H02M2001/0032 ,  Y02B70/1466 ,  Y02B70/16

Abstract: A DC-DC converter transitions between continuous conduction mode (CCM) and discontinuous conduction mode (DCM) without causing any overshoot or undershoot deviation output voltage. The DC-DC converter operates in a PWM mode in CCM. During DCM, it skips PWM pulses when a sustained negative current is detected in an output inductor. The current sensing is achieved by sampling and integrating a voltage, the sign of which is inverse to current direction. The sample and hold and integrator circuits are small, simple, and scale to high frequencies. The pulse skipping circuit automatically adjusts the duty cycle of power pulses to force a zero inductor current at the end of each pulse.

Abstract translation: DC-DC转换器在连续导通模式（CCM）和不连续导通模式（DCM）之间转换，而不会引起任何过冲或下冲偏差输出电压。 DC-DC转换器在CCM中以PWM模式工作。 在DCM期间，当在输出电感中检测到持续的负电流时，它会跳过PWM脉冲。 电流检测通过采样和积分一个电压来实现，该电压的符号与当前方向相反。 采样和保持和积分电路小巧，简单，并可扩展到高频。 脉冲跳跃电路自动调整功率脉冲的占空比，以在每个脉冲结束时强制产生零电感电流。

公开(公告)号：US20160056830A1

公开(公告)日：2016-02-25

申请号：US14930708

申请日：2015-11-03

Applicant: STMicroelectronics International N.V.

Inventor： Rakesh Malik ,  Chandrajit Debnath ,  Ashish Sharma Kumar ,  Pratap Narayan Singh

IPC: H03M1/12 ,  H03M1/46 ,  H03M1/06

CPC classification number: H03M1/125 ,  H03M1/00 ,  H03M1/0612 ,  H03M1/069 ,  H03M1/0695 ,  H03M1/12 ,  H03M1/46 ,  H03M1/462

Abstract: An asynchronous SAR ADC converts an analog signal into a series of digital pulses in an efficient, low power manner. In synchronous SAR ADC circuits, a separate and cumbersome clock signal is used to trigger the internal circuitry of the SAR ADC. Instead of triggering the components of the SAR DAC synchronously with a clock signal, the asynchronous solution uses its own internal signals to trigger its components in an asynchronous cyclic manner. Further, in order to increase efficiency and guard against circuit failures due to difficulties arising from transient signals, the asynchronous SAR ADC may also include a delay circuit for introducing a variable delay to the SAR ADC cycle.

Abstract translation: 异步SAR ADC以有效，低功耗的方式将模拟信号转换为一系列数字脉冲。 在同步SAR ADC电路中，单独和繁琐的时钟信号用于触发SAR ADC的内部电路。 异步解决方案不是以时钟信号同步触发SAR DAC的组件，而是以其自身的内部信号以异步循环方式触发其组件。 此外，为了提高效率并防止由于瞬态信号引起的困难而导致的电路故障，异步SAR ADC还可以包括用于将可变延迟引入SAR ADC周期的延迟电路。

公开(公告)号：US20160049189A1

公开(公告)日：2016-02-18

申请号：US14813278

申请日：2015-07-30

Applicant: STMicroelectronics SA ,  STMicroelectronics International N.V.

Inventor： Christophe Lecocq ,  Kaya Can Akyel ,  Amit Chhabra ,  Dibya Dipti

IPC: G11C11/417

CPC classification number: G11C11/417 ,  G11C11/412 ,  H01L27/1104

Abstract: An SRAM cell is formed of FDSOI-type NMOS and PMOS transistors. A doped well extends under the NMOS and PMOS transistors and is separated therefrom by an insulating layer. A bias voltage is applied to the doped well. The applied bias voltage is adjusted according to a state of the memory cell. For example, a temperature of the memory cell is sensed and the bias voltage adjusted as a function of the sensed temperature. The adjustment in the bias voltage is configured so that threshold voltages of the NMOS and PMOS transistors are substantially equal to n and p target threshold voltages, respectively.

Abstract translation: SRAM单元由FDSOI型NMOS和PMOS晶体管形成。 掺杂阱在NMOS和PMOS晶体管的下方延伸，并通过绝缘层与其分离。 偏置电压施加到掺杂阱。 施加的偏置电压根据存储单元的状态进行调整。 例如，感测存储器单元的温度，并根据检测到的温度调整偏置电压。 偏置电压的调整被配置为使得NMOS和PMOS晶体管的阈值电压分别基本上等于n和p个目标阈值电压。

公开(公告)号：US09264045B2

公开(公告)日：2016-02-16

申请号：US14231939

申请日：2014-04-01

Applicant: STMicroelectronics International N.V.

Inventor： Sameer Vashishtha ,  Saiyid Mohammad Irshad Rizvi

IPC: H03K5/08 ,  H03K19/0948 ,  H03K19/003 ,  H03K19/0185 ,  H03K19/00

CPC classification number: H03K19/09487 ,  H03K19/0027 ,  H03K19/00361 ,  H03K19/018521

Abstract: A buffer includes an input configured to receive a first digital signal having first and second logic states referenced, respectively, to a first high voltage and a first low voltage of a first supply domain. A first inverter circuit includes a pMOS transistor and nMOS transistor having gate terminals connected to the input. A second inverter is connected in series with the output of the first inverter. The second inverter has an output configured to generate a second digital signal having first and second logic states referenced, respectively, to a second high voltage and a second low voltage of a second, different, supply domain, wherein at least the second high voltage is greater than the first high voltage. A feedback circuit is configured to apply the second digital signal as a bias to a transistor body of the p-MOS transistor of the first inverter circuit.

Abstract translation: 缓冲器包括被配置为接收具有分别被引用到第一供电域的第一高电压和第一低电压的第一和第二逻辑状态的第一数字信号的输入。 第一反相器电路包括具有连接到输入的栅极端子的pMOS晶体管和nMOS晶体管。 第二反相器与第一反相器的输出串联。 第二反相器具有被配置为产生具有第一和第二逻辑状态的第二数字信号的第二数字信号，第一和第二逻辑状态分别被称为第二高电压和第二不同供电域的第二低电压，其中至少第二高电压是 大于第一高电压。 反馈电路被配置为将第二数字信号作为偏置施加到第一反相器电路的p-MOS晶体管的晶体管本体。