公开(公告)号：US11476410B2

公开(公告)日：2022-10-18

申请号：US16997922

申请日：2020-08-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Chun Chen ,  Yen-Chun Liu ,  Ya-Sheng Feng ,  Chiu-Jung Chiu ,  I-Ming Tseng ,  Yi-An Shih ,  Yi-Hui Lee ,  Chung-Liang Chu ,  Hsiu-Hao Hu

IPC: H01L43/02 ,  H01L43/12 ,  H01L27/22 ,  H01L43/10

Abstract: A semiconductor device includes a substrate having a magnetic random access memory (MRAM) region and a logic region, a first metal interconnection on the MRAM region, a second metal interconnection on the logic region, a stop layer extending from the first metal interconnection to the second metal interconnection, and a magnetic tunneling junction (MTJ) on the first metal interconnection. Preferably, the stop layer on the first metal interconnection and the stop layer on the second metal interconnection have different thicknesses.

公开(公告)号：US11476192B2

公开(公告)日：2022-10-18

申请号：US16734373

申请日：2020-01-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Chia-Huei Lin ,  Kuo-Yuh Yang

IPC: H01L23/528 ,  H01L29/08 ,  H01L29/78 ,  H01L27/12 ,  H01L29/423 ,  H01L29/45 ,  H01L21/768 ,  H03F3/16 ,  H01L21/321 ,  H01L21/84

Abstract: A semiconductor device includes: a first gate line and a second gate line extending only along a first direction, a third gate line and a fourth gate line extending along the first direction and between the first gate line and the second gate line, a fifth gate line and a sixth gate line extending along a second direction between the first gate line and the second gate line and intersecting the third gate line and the fourth gate line, and first contact plugs on the first gate line. Preferably, the first direction is perpendicular to the second direction and the first gate line and the second gate line are directly connected to the fifth gate line and the sixth gate line.

公开(公告)号：US20220328685A1

公开(公告)日：2022-10-13

申请号：US17852371

申请日：2022-06-29

Applicant: United Microelectronics Corp.

Inventor： Tseng Hsun Liu ,  Min-Hsuan Tsai ,  Ke-Feng Lin ,  Ming-Yen Liu ,  Wen-Chung Chang ,  Cherng-En Sun

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/423

Abstract: A method for fabricating a transistor includes providing a substrate, having a gate region and a first trench in the substate at a first side of the gate region; forming a first gate insulating layer, disposed on a first portion of the gate region, opposite to the first trench; forming a second gate insulating layer, disposed on a second portion of the gate region and a first portion of the first trench abutting to the gate region, wherein the second gate insulating layer is thicker than the first gate insulating layer; forming a gate layer, disposed on the first and second gate insulating layers, having a downward protruding portion corresponding to the first trench; forming a first doped region in the substrate at least under the first trench; and forming a second doped region in the substrate at a second side of the gate region.

公开(公告)号：US20220320849A1

公开(公告)日：2022-10-06

申请号：US17223767

申请日：2021-04-06

Applicant: United Microelectronics Corp.

Inventor： Chih-Yuan Chung ,  Te-Chang Wu

IPC: H02H3/08 ,  H02H3/06

Abstract: An electrostatic discharge (ESD) circuit is used to protect an internal circuit. The ESD circuit includes: an ESD clamp, having a first terminal connected to a power and a second terminal connected to a ground voltage; and a first switch, connected between an ESD terminal of the ESD clamp and the internal circuit. A gate of the first switch is controlled by a state signal in the ESD clamp to turn off the first switch when an ESD event occurs on the first terminal of the ESD clamp and turn on the first switch when the ESD event does not occur.

公开(公告)号：US20220320292A1

公开(公告)日：2022-10-06

申请号：US17683288

申请日：2022-02-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ming Hsu ,  Yu-Chi Wang ,  Yen-Hsing Chen ,  Tsung-Mu Yang ,  Yu-Ren Wang

IPC: H01L29/15 ,  H01L29/778

Abstract: A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.

公开(公告)号：US11462489B2

公开(公告)日：2022-10-04

申请号：US17401335

申请日：2021-08-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Kuo-Yuh Yang ,  Chia-Huei Lin ,  Chu-Chun Chang

IPC: H01L23/00 ,  H01L27/12 ,  H01L21/84 ,  H01L23/58 ,  H01L23/66 ,  H01L27/06

Abstract: A method of forming integrated circuit device, including: providing a substrate; forming an integrated circuit region on the substrate, the integrated circuit region comprising a dielectric stack; forming a seal ring in the dielectric stack and around a periphery of the integrated circuit region; forming a trench around the seal ring and the trench exposing a sidewall of the dielectric stack; forming a moisture blocking layer continuously covering the integrated circuit region and extending to the sidewall of the dielectric stack, thereby sealing a boundary between two adjacent dielectric films in the dielectric stack; and forming a passivation layer over the moisture blocking layer.

公开(公告)号：US11462441B2

公开(公告)日：2022-10-04

申请号：US17147477

申请日：2021-01-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Wei Su ,  Hao-Che Feng ,  Hsuan-Tai Hsu ,  Chun-Yu Chen ,  Wei-Hao Huang ,  Bin-Siang Tsai ,  Ting-An Chien

IPC: H01L21/8234 ,  H01L21/762 ,  H01L21/02 ,  H01L29/66 ,  H01L29/786 ,  H01L29/775 ,  H01L29/06 ,  H01L21/3065

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a fin-shaped structure on a substrate, forming a dielectric layer surrounding the fin-shaped structure, performing an anneal process to transform the dielectric layer into a shallow trench isolation (STI), removing the fin-shaped structure to form a trench, and forming a stack structure in the trench. Preferably, the stack structure includes a first semiconductor layer on the fin-shaped structure and a second semiconductor layer on the first semiconductor layer and the first semiconductor layer and the second semiconductor layer include different materials.

公开(公告)号：US11456207B2

公开(公告)日：2022-09-27

申请号：US16518928

申请日：2019-07-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Chih Chang ,  Yuan-Fu Ko ,  Chih-Sheng Chang

IPC: H01L21/768 ,  H01L23/528 ,  H01L21/02 ,  H01L23/532

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a first metal interconnection in the first IMD layer; removing part of the first IMD layer; forming a spacer adjacent to the first metal interconnection; forming a second IMD layer on the spacer and the first metal interconnection; and forming a second metal interconnection in the second IMD layer and on the spacer and the first metal interconnection.

公开(公告)号：US20220302118A1

公开(公告)日：2022-09-22

申请号：US17230975

申请日：2021-04-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Kun-Hsien Lee ,  Sheng-Yuan Hsueh ,  Chang-Chien Wong ,  Ching-Hsiang Tseng ,  Tsung-Hsun Wu ,  Chi-Horn Pai ,  Shih-Chieh Hsu

IPC: H01L27/108

Abstract: The invention provides a semiconductor memory cell, the semiconductor memory cell includes a substrate having a first conductivity type, a doped region in the substrate, wherein the doped region has a second conductivity type, and the first conductivity type is complementary to the second conductivity type, a capacitor insulating layer and an upper electrode on the doped region, a transistor on the substrate, and a shallow trench isolation disposed between the transistor and the capacitor insulating layer, and the shallow trench isolation is disposed in the doped region.

公开(公告)号：US11450564B2

公开(公告)日：2022-09-20

申请号：US16568266

申请日：2019-09-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jin-Yan Chiou ,  Wei-Chuan Tsai ,  Yen-Tsai Yi ,  Li-Han Chen ,  Hsiang-Wen Ke

IPC: H01L21/768 ,  H01L29/66 ,  H01L21/285

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a source/drain region adjacent to two sides of the gate structure; forming an interlayer dielectric (ILD) layer on the gate structure; forming a contact hole in the ILD layer to expose the source/drain region; forming a barrier layer in the contact hole; performing an anneal process; and performing a plasma treatment process to inject nitrogen into the contact hole.