公开(公告)号：US20140252507A1

公开(公告)日：2014-09-11

申请号：US13785938

申请日：2013-03-05

Applicant: STMICROELECTRONICS PTE LTD.

Inventor： Ravi Shankar ,  Olivier Le Neel ,  Shian Yeu Kam ,  Tien Choy Loh

IPC: B81C1/00 ,  B81B7/00

CPC classification number: B81C1/00293 ,  B81B7/0041 ,  B81C2203/0136

Abstract: Embodiments of the present disclosure are related to MEMS devices having a suspended membrane that are secured to and spaced apart from a substrate with a sealed cavity therebetween. The membrane includes openings with sidewalls that are closed by a dielectric material. In various embodiments, the cavity between the membrane and the substrate is formed by removing a sacrificial layer through the openings. In one or more embodiments, the openings in the membrane are closed by depositing the dielectric material on the sidewalls of the openings and the upper surface of the membrane.

Abstract translation: 本公开的实施例涉及具有悬置膜的MEMS器件，其被固定到衬底上并与衬底间隔开密封腔。 膜包括具有由介电材料封闭的侧壁的开口。 在各种实施例中，通过从开口去除牺牲层来形成膜与衬底之间的空腔。 在一个或多个实施例中，通过将介电材料沉积在开口的侧壁和膜的上表面上来封闭膜中的开口。

公开(公告)号：US08786396B2

公开(公告)日：2014-07-22

申请号：US13339968

申请日：2011-12-29

Applicant: Calvin Leung ,  Olivier Le Neel

Inventor： Calvin Leung ,  Olivier Le Neel

IPC: H01C3/04

CPC classification number: H01C17/265 ,  H01C17/267 ,  H01L23/345 ,  H01L23/5228 ,  H01L24/05 ,  H01L27/016 ,  H01L27/0688 ,  H01L28/20 ,  H01L2924/01019 ,  H01L2924/1301 ,  H01L2924/13033 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00

Abstract: A heater design for post-process trimming of thin-film transistors is described. The heater incorporates low sheet-resistance material deposited in non-active connecting regions of the heater to reduce heat generation and power consumption in areas distant from active heating members of the heater. The heating members are proximal to a thin-film resistor. The resistance of the thin-film resistor can be trimmed permanently to a desired value by applying short current pulses to the heater. Optimization of a heater design is described. Trimming currents can be as low as 20 mA.

Abstract translation: 描述了用于薄膜晶体管的后处理修整的加热器设计。 加热器包含沉积在加热器的非活动连接区域中的低片材阻力材料，以减少远离加热器的主动加热构件的区域中的发热和功率消耗。 加热件靠近薄膜电阻。 通过向加热器施加短电流脉冲，可以将薄膜电阻器的电阻永久地修整到所需的值。 描述加热器设计的优化。 微调电流可以低至20 mA。

公开(公告)号：US20140113410A1

公开(公告)日：2014-04-24

申请号：US13655036

申请日：2012-10-18

Applicant: STMICROELECTRONICS PTE LTD.

Inventor： How Yuan Hwang ,  Jay Maghirang ,  Yaohuang Huang ,  Kim-Yong Goh ,  Phone Maw Hla ,  Edmond Soon

IPC: H01L21/60

CPC classification number: H01L21/561 ,  H01L21/568 ,  H01L24/11 ,  H01L24/13 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/81 ,  H01L24/92 ,  H01L24/96 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16265 ,  H01L2224/17181 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/8121 ,  H01L2224/8123 ,  H01L2224/81815 ,  H01L2224/9211 ,  H01L2224/96 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2224/19 ,  H01L2224/81 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are related to manufacturing system-in-packages at wafer-level. In particular, various embodiments are directed to adhering a first wafer to a second wafer and adhering solder balls to contact pads of the first wafer. In one embodiment, a first wafer having first and second surfaces is provided. The first wafer includes bond pads located on the first surface that are coupled to a respective semiconductor device located in the first wafer. A second wafer having an electrical component located therein is provided. A conductive adhesive is provided on at least one of the first wafer and the second wafer. Conductive balls are provided on the bond pads on the first surface of the first wafer. The conductive balls and the conductive adhesive are heated to cause the conductive balls to adhere to the bond pad and the conductive adhesive to adhere the first wafer to the second wafer.

Abstract translation: 本公开的实施例涉及在晶片级制造系统级封装。 具体地，各种实施例涉及将第一晶片粘附到第二晶片并将焊球粘附到第一晶片的接触焊盘。 在一个实施例中，提供具有第一和第二表面的第一晶片。 第一晶片包括位于第一表面上的接合焊盘，其耦合到位于第一晶片中的相应半导体器件。 提供了具有位于其中的电气部件的第二晶片。 在第一晶片和第二晶片中的至少一个上提供导电粘合剂。 导电球设置在第一晶片的第一表面上的接合焊盘上。 导电球和导电粘合剂被加热以使导电球粘附到接合焊盘和导电粘合剂以将第一晶片粘附到第二晶片。

公开(公告)号：US20140103521A1

公开(公告)日：2014-04-17

申请号：US13652937

申请日：2012-10-16

Applicant: STMICROELECTRONICS PTE. LTD

Inventor： Yonggang Jin ,  How Yuan HWANG

IPC: H01L23/498 ,  H01L21/56

CPC classification number: H01L23/49811 ,  H01L21/56 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/19 ,  H01L25/03 ,  H01L25/105 ,  H01L2224/12105 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/18162 ,  H01L2924/00

Abstract: An electronic device may include a bottom interconnect layer and an integrated circuit (IC) carried by the bottom interconnect layer. The electronic device may further include an encapsulation material on the bottom interconnect layer and laterally surrounding the IC. The electronic device may further include electrically conductive pillars on the bottom interconnect layer extending through the encapsulation material. At least one electrically conductive pillar and adjacent portions of encapsulation material may have a reduced height with respect to adjacent portions of the IC and the encapsulation material and may define at least one contact recess. The at least one contact recess may be spaced inwardly from a periphery of the encapsulation material.

Abstract translation: 电子设备可以包括底部互连层和由底部互连层承载的集成电路（IC）。 电子设备还可以包括底部互连层上的封装材料并横向包围IC。 电子器件还可以包括穿过封装材料的底部互连层上的导电柱。 至少一个导电柱和封装材料的相邻部分可以相对于IC和封装材料的相邻部分具有减小的高度，并且可以限定至少一个接触凹部。 所述至少一个接触凹部可以与所述封装材料的周边向内间隔开。

公开(公告)号：US20140091443A1

公开(公告)日：2014-04-03

申请号：US14032075

申请日：2013-09-19

Applicant: STMicroelectronics Pte Ltd ,  STMicroelectronics (Malta) Ltd

Inventor： Roseanne Duca ,  Kim-Yong Goh ,  Xueren Zhang ,  Kevin Formosa

IPC: H01L23/495 ,  H01L21/56

CPC classification number: H01L23/49541 ,  G01P1/023 ,  H01L21/56 ,  H01L21/565 ,  H01L23/3107 ,  H01L2224/45147 ,  H01L2224/48247 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/1461 ,  H01L2924/1815 ,  H05K3/303 ,  H05K3/3421 ,  H05K2201/09781 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/01005 ,  H01L2224/45099

Abstract: A surface mount package of a semiconductor device, has: an encapsulation, housing at least one die including semiconductor material; and electrical contact leads, protruding from the encapsulation to be electrically coupled to contact pads of a circuit board; the encapsulation has a main face designed to face a top surface of the circuit board, which is provided with coupling features designed for mechanical coupling to the circuit board to increase a resonant frequency of the mounted package. The coupling features envisage at least a first coupling recess defined within the encapsulation starting from the main face, designed to be engaged by a corresponding coupling element fixed to the circuit board, thereby restricting movements of the mounted package.

Abstract translation: 半导体器件的表面贴装封装具有：封装，容纳至少一个包含半导体材料的管芯; 以及电接触引线，从封装凸出以电耦合到电路板的接触焊盘; 封装具有设计成面向电路板的顶表面的主面，该主面具有设计成用于机械耦合到电路板的耦合特征，以增加安装封装的谐振频率。 耦合特征设想至少一个第一耦合凹槽，其限定在从主面开始的封装内，被设计成由固定到电路板的对应耦合元件接合，从而限制安装的封装的移动。

公开(公告)号：US20140054727A1

公开(公告)日：2014-02-27

申请号：US13595933

申请日：2012-08-27

Applicant: Hong-Gap Chua ,  Yee-Chung Chan ,  Mei-Yu Muk

Inventor： Hong-Gap Chua ,  Yee-Chung Chan ,  Mei-Yu Muk

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/66575 ,  H01L21/2255 ,  H01L29/78

Abstract: A method of forming a transistor is disclosed, in which gate-to-substrate leakage is addressed by forming and maintaining a conformal oxide layer overlying the transistor gate. Using the method disclosed for an n-type device, the conformal oxide layer can be formed as part of the source-drain doping process. Subsequent removal of residual phosphorous dopants from the surface of the oxide layer is accomplished without significant erosion of the oxide layer. The removal step uses a selective deglazing process that employs a hydrolytic reaction, and an acid-base neutralization reaction that includes an ammonium hydroxide component.

Abstract translation: 公开了一种形成晶体管的方法，其中通过形成和维持覆盖晶体管栅极的共形氧化物层来解决栅极到衬底的泄漏。 使用公开的用于n型器件的方法，保形氧化物层可以形成为源 - 漏掺杂工艺的一部分。 随后从氧化物层的表面除去残留的磷掺杂剂，而不会明显地侵蚀氧化物层。 除去步骤使用采用水解反应的选择性脱气方法和包含氢氧化铵组分的酸碱中和反应。

公开(公告)号：US08659085B2

公开(公告)日：2014-02-25

申请号：US12862589

申请日：2010-08-24

Applicant: Hui Chong Vince Ng ,  Olivier Le Neel ,  Calvin Leung

Inventor： Hui Chong Vince Ng ,  Olivier Le Neel ,  Calvin Leung

IPC: H01L21/02

CPC classification number: H01L23/5228 ,  H01L21/76834 ,  H01L21/76852 ,  H01L28/20 ,  H01L2221/1078 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure is directed to an integrated circuit having a substrate and a first and a second interconnect structure over the substrate. Each interconnect structure has a first conductive layer over the substrate and a second conductive layer over the first conductive layer. The integrated circuit also includes a thin film resistor over a portion of the substrate between the first and the second interconnect structure that electrically connects the first conductive layers of the first and second interconnect structures.

Abstract translation: 本发明涉及一种集成电路，该集成电路具有衬底和衬底上的第一和第二互连结构。 每个互连结构在衬底上具有第一导电层，并且在第一导电层上方具有第二导电层。 集成电路还包括在第一和第二互连结构之间的衬底的一部分上的薄膜电阻器，其电连接第一和第二互连结构的第一导电层。

公开(公告)号：US08644053B2

公开(公告)日：2014-02-04

申请号：US13953626

申请日：2013-07-29

Applicant: STMicroelectronics Pte Ltd.

Inventor： Olivier Le Neel

IPC: G11C11/00

CPC classification number: G11C13/0002 ,  G11C11/21 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/008 ,  G11C2213/33 ,  G11C2213/71

Abstract: An integrated circuit is formed having an array of memory cells located in the dielectric stack above a semiconductor substrate. Each memory cell has two adjustable resistors and two heating elements. A dielectric material separates the heating elements from the adjustable resistors. One heating element alters the resistance of one of the resistors by applying heat thereto to write data to the memory cell. The other heating element alters the resistance of the other resistor by applying heat thereto to erase data from the memory cell.

Abstract translation: 形成集成电路，其具有位于半导体衬底上方的电介质堆叠中的存储器单元的阵列。 每个存储单元具有两个可调电阻器和两个加热元件。 电介质材料将加热元件与可调电阻分开。 一个加热元件通过加热来改变其中一个电阻器的电阻以将数据写入存储单元。 另一个加热元件通过加热来改变另一个电阻器的电阻，从而擦除来自存储单元的数据。

公开(公告)号：US08637352B2

公开(公告)日：2014-01-28

申请号：US13302602

申请日：2011-11-22

Applicant: Kim-Yong Goh

Inventor： Kim-Yong Goh

IPC: H01L21/00

CPC classification number: H01L24/97 ,  B23K1/0016 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00

Abstract: Ball grid array to pin grid array conversion methods are provided. An example method can include coupling a plurality of solder balls to a respective plurality of pin grid array contact pads. Each of the plurality of solder balls is encapsulated in a fixed material. A portion of the plurality of solder balls and a portion of the fixed material is removed to provide a plurality of exposed solder balls. The exposed solder balls are softened and each of a plurality of pin members is inserted in a softened, exposed, solder ball. The plurality of pin members forms a pin grid array package.

Abstract translation: 提供球栅阵列引脚网格阵列转换方法。 示例性方法可以包括将多个焊球耦合到相应的多个引脚栅极阵列接触焊盘。 多个焊球中的每一个被封装在固定材料中。 多个焊球的一部分和固定材料的一部分被去除以提供多个暴露的焊球。 暴露的焊球被软化，并且多个销构件中的每一个插入软化的暴露的焊球中。 多个销构件形成销栅格阵列封装。

公开(公告)号：US08617987B2

公开(公告)日：2013-12-31

申请号：US12982697

申请日：2010-12-30

Applicant: Kah Wee Gan ,  Yonggang Jin ,  Yun Liu ,  Yaohuang Huang

Inventor： Kah Wee Gan ,  Yonggang Jin ,  Yun Liu ,  Yaohuang Huang

IPC: H01L21/44 ,  H01L21/48

CPC classification number: H01L25/105 ,  H01L21/486 ,  H01L21/568 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/181 ,  Y10T29/413 ,  Y10T29/49144 ,  Y10T29/49165 ,  H01L2924/00

Abstract: An embedded wafer level ball grid array (eWLB) is formed by embedding a semiconductor die in a molding compound. A trench is formed in the molding compound with a laser drill. A first layer of copper is deposited on the sidewall of the trench by physical vapor deposition. A second layer of copper is then formed on the first layer of copper by an electroless process. A third layer of copper is then formed on the second layer by electroplating.

Abstract translation: 嵌入式晶片级球栅阵列（eWLB）通过将半导体管芯嵌入到模塑料中而形成。 在激光钻头的模塑料中形成沟槽。 第一层铜通过物理气相沉积沉积在沟槽的侧壁上。 然后通过无电解方法在第一层铜上形成第二层铜层。 然后通过电镀在第二层上形成第三层铜层。