公开(公告)号：US09000963B2

公开(公告)日：2015-04-07

申请号：US14293119

申请日：2014-06-02

Applicant: STMicroelectronics SA ,  STMicroelectronics International N.V.

Inventor： Pratap Narayan Singh ,  Stéphane Le Tual

IPC: H03M1/00 ,  H03K17/22 ,  H03M1/12 ,  H03K17/14 ,  H03K17/687

CPC classification number: H03K17/223 ,  H03K17/145 ,  H03K17/687 ,  H03K2217/0018 ,  H03M1/12

Abstract: The invention concerns a circuit comprising: a first transistor (102) having first and second main current nodes, and a gate node adapted to receive a first timing signal (CLK) for causing the first transistor to transition between conducting and non-conducting states; a biasing circuit (108) coupled to a further node of said first transistor; and a control circuit (110) adapted to control said biasing circuit to apply a first control voltage (VCTRL) to said further node to adjust the timing of at least one of said transitions.

Abstract translation: 本发明涉及一种电路，包括：具有第一和第二主电流节点的第一晶体管（102）和适于接收用于使第一晶体管在导通状态与非导通状态之间转变的第一定时信号（CLK）的栅极节点; 偏置电路（108），耦合到所述第一晶体管的另一节点; 以及适于控制所述偏置电路以对所述另一节点施加第一控制电压（VCTRL）以调整至少一个所述转换的定时的控制电路（110）。

公开(公告)号：US09000826B2

公开(公告)日：2015-04-07

申请号：US14280807

申请日：2014-05-19

Applicant: STMicroelectronics International N.V.

Inventor： Adeel Ahmad ,  Chandrajit Debnath

IPC: H03L5/00 ,  H03F3/45 ,  H03K19/0185

CPC classification number: H03L5/00 ,  H03F3/45179 ,  H03K19/018528

Abstract: An amplifier has a first pull-up path coupled between a voltage supply node and an output node, and a pull-down path coupled between the output node and a ground supply node. A second pull-up path is coupled between the voltage supply node and the output node. The second pull-up path is actuated by a feedback signal and biased by a biasing signal. An inverter circuit is operable to invert the signal at the amplifier output node to generate the feedback signal. A biasing circuit is configured to generate the biasing signal. The biasing circuit is configured to control a relative strength of the pull-down path to the second pull-up path, wherein the pull-down path is stronger than the second pull-up path in a manner that is consistently present over all PVT corners.

Abstract translation: 放大器具有耦合在电压供应节点和输出节点之间的第一上拉通路，以及耦合在输出节点和地电源节点之间的下拉通路。 第二上拉路径耦合在电压供应节点和输出节点之间。 第二上拉路径由反馈信号驱动并被偏置信号偏置。 反相器电路可操作以反转放大器输出节点处的信号以产生反馈信号。 偏置电路被配置为产生偏置信号。 偏置电路被配置为控制到第二上拉路径的下拉路径的相对强度，其中下拉路径以一致地存在于所有PVT角上的方式比第二上拉路径更强 。

公开(公告)号：US20150078069A1

公开(公告)日：2015-03-19

申请号：US14478477

申请日：2014-09-05

Applicant: STMicroelectronics International N.V.

Inventor： Jacques Talayssat

IPC: G11C11/419 ,  H01L27/11 ,  G11C8/10

CPC classification number: G11C11/419 ,  G11C8/10 ,  H01L21/761 ,  H01L21/823892 ,  H01L27/0928 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1104

Abstract: An integrated circuit includes first and second circuit parts that may be arranged close to one another in a single semiconducting substrate. The circuit may use a deep doping well for reducing digital noise, and may implement a sleep mode for reducing power consumption. This circuit may have a random access memory, and may be a radio communication system-on-chip device. The integrated circuit may advantageously be used within a mobile communication apparatus.

Abstract translation: 集成电路包括可以在单个半导体衬底中彼此靠近布置的第一和第二电路部分。 电路可以使用深掺杂阱来减少数字噪声，并且可以实现睡眠模式以降低功耗。 该电路可以具有随机存取存储器，并且可以是无线电通信片上系统设备。 集成电路可以有利地在移动通信设备内使用。

公开(公告)号：US08982651B2

公开(公告)日：2015-03-17

申请号：US13852222

申请日：2013-03-28

Applicant: STMicroelectronics International N.V.

Inventor： Anuj Grover ,  Gangaikondan Subramani Visweswaran

IPC: G11C7/00 ,  G11C7/02 ,  G11C7/06

CPC classification number: G11C7/06 ,  G11C7/14 ,  G11C11/419 ,  G11C17/18

Abstract: A memory includes an array of active memory cells arranged in rows and columns, and at least one dummy memory cell column adjacent the array of active memory cells. A sensing circuit is coupled to the at least one dummy memory cell column to sense at least one variation associated with the at least one dummy memory cell column. An assist circuit is coupled to the array of active memory cells. An assist determination controller is coupled to the sensing circuit to store a look-up table of output assist values corresponding to different variations associated with the at least one dummy memory cell column, to determine an output assist value from the look-up table based upon the at least sensed variation, and to operate the assist circuit based upon the determined output assist value.

Abstract translation: 存储器包括以行和列布置的活动存储单元的阵列，以及与活动存储器单元阵列相邻的至少一个虚拟存储单元列。 感测电路耦合到所述至少一个虚拟存储器单元列以感测与所述至少一个虚拟存储器单元列相关联的至少一个变化。 辅助电路耦合到有源存储器单元阵列。 辅助确定控制器耦合到感测电路以存储对应于与至少一个虚拟存储器单元列相关联的不同变化的输出辅助值的查找表，以基于查找表来确定来自查找表的输出辅助值 至少感测到的变化，并且基于所确定的输出辅助值来操作辅助电路。

公开(公告)号：US20150061621A1

公开(公告)日：2015-03-05

申请号：US14018967

申请日：2013-09-05

Applicant: STMicroelectronics International N.V.

Inventor： Alexandre PONS

IPC: G05F1/56

CPC classification number: G05F1/56 ,  G05F1/575

Abstract: A circuit including a low drop-out regulator (LDO) has a current control loop configured and connected to detect whether an external capacitor is connected to the output of the LDO. The current control loop includes a differential amplifier, a current source capable to output different reference currents and a small MOS transistor. The circuit may be operated in an output capacitor detection mode when started and in a regulated voltage source mode otherwise. In the output capacitor detection mode, the small MOS transistor is driven by the differential amplifier and drives the LDO's power MOS transistor depending on a difference between a current through the small MOS transistor and the reference current output by the current source. Components of the current control loop may be used during regulated voltage source mode for short circuit protection.

Abstract translation: 包括低压差稳压器（LDO）的电路具有配置和连接的电流控制回路，以检测外部电容器是否连接到LDO的输出端。 电流控制回路包括差分放大器，能够输出不同参考电流的电流源和小型MOS晶体管。 电路可以在启动时以输出电容器检测模式工作，否则在稳压电源模式下工作。 在输出电容检测模式下，小型MOS晶体管由差分放大器驱动，并根据通过小MOS晶体管的电流与电流源输出的参考电流之间的差异驱动LDO的功率MOS晶体管。 电流控制回路的组件可在调节电压源模式下用于短路保护。

公开(公告)号：US20150058578A1

公开(公告)日：2015-02-26

申请号：US14464750

申请日：2014-08-21

Applicant: STMicroelectronics International N.V.

Inventor： Gilles Ries ,  Ennio Salemi ,  Sana Ben Alaya

IPC: G06F12/08 ,  G06F12/10

CPC classification number: G06F12/0862 ,  G06F12/1027 ,  G06F12/1063 ,  G06F2212/304 ,  G06F2212/507 ,  G06F2212/602 ,  G06F2212/684

Abstract: A memory management unit may send page table walk requests to a page table descriptor in a main memory system and receive address translation information, with the page table walk requests including information that specifies an amount of further address translation information, and receive the further address translation information. The cache unit may intercept the page table walk requests, and modify content of the intercepted page table walk requests so the information that specifies the amount of further address translation information is extended from a first amount to a second amount greater than the first amount. The cache unit may store the second amount of further address translation information for use with data requests that are subsequent to a current data request, and provide the address translation information based upon an intercepted page table walk request being associated with address translation information already stored in the cache unit.

Abstract translation: 存储器管理单元可以将页面表移动请求发送到主存储器系统中的页表描述符并且接收地址转换信息，其中页表步行请求包括指定进一步的地址转换信息的量的信息，并且接收另外的地址转换 信息。 高速缓存单元可以拦截页表行走请求，并且修改被拦截的页表行走请求的内容，使得指定进一步的地址转换信息量的信息从第一数量扩展到大于第一数量的第二数量。 高速缓存单元可以存储第二数量的进一步的地址转换信息，以便与当前数据请求之后的数据请求一起使用，并且基于与已经存储在地址转换信息中的地址转换信息相关联的被拦截的页表移动请求来提供地址转换信息 缓存单元。

公开(公告)号：US20150042301A1

公开(公告)日：2015-02-12

申请号：US13962958

申请日：2013-08-09

Applicant: STMicroelectronics International N.V.

Inventor： Rajesh NARWAL

IPC: G05F3/08 ,  G05F1/46

CPC classification number: G05F3/08 ,  G05F1/46 ,  G05F1/462 ,  G05F1/468 ,  G05F1/56 ,  G05F1/565 ,  H02M2001/0025

Abstract: An embodiment of an arrangement includes a voltage regulator configured to provide an output voltage, said voltage regulator configured to receive one of a plurality of different regulator reference voltages and a controller configured to provide a selection signal, said selection signal being used to control which of said regulator reference voltages said voltage regulator receives.

Abstract translation: 布置的实施例包括被配置为提供输出电压的电压调节器，所述电压调节器被配置为接收多个不同调节器参考电压中的一个，以及被配置为提供选择信号的控制器，所述选择信号用于控制 所述稳压器所述电压调节器的参考电压接收。

公开(公告)号：US20150028930A1

公开(公告)日：2015-01-29

申请号：US14337896

申请日：2014-07-22

Applicant: STMicroelectronics SA ,  STMicroelectronics International N.V.

Inventor： Stéphane Le Tual ,  Pratap Narayan Singh

IPC: H03H11/26

CPC classification number: H03K5/134 ,  H03K5/13 ,  H03K2005/00032 ,  H03K2005/00208 ,  H03K2005/00215 ,  H03K2217/0018

Abstract: A delay circuit includes first and second transistors and a biasing circuit. The first transistor has a control node coupled to an input node of the delay circuit, a first main current node coupled to a first supply voltage, and a second main current node coupled to an output node of the delay circuit. A second transistor has a control node coupled to the input node, a first main current node coupled to a second supply voltage, and a second main current node coupled to the output node. The biasing circuit is configured to generate first and second differential control voltages , to apply the first differential control voltage to a further control node of the first transistor and to apply the second differential control voltage to a further control node of the second transistor.

Abstract translation: 延迟电路包括第一和第二晶体管和偏置电路。 第一晶体管具有耦合到延迟电路的输入节点的控制节点，耦合到第一电源电压的第一主电流节点和耦合到延迟电路的输出节点的第二主电流节点。 第二晶体管具有耦合到输入节点的控制节点，耦合到第二电源电压的第一主电流节点和耦合到输出节点的第二主电流节点。 偏置电路被配置为产生第一和第二差分控制电压，以将第一差分控制电压施加到第一晶体管的另一控制节点，并将第二差分控制电压施加到第二晶体管的另一个控制节点。

公开(公告)号：US08942502B2

公开(公告)日：2015-01-27

申请号：US13963860

申请日：2013-08-09

Applicant: STMicroelectronics International N.V.

Inventor： Surinder Pal Singh ,  Aneesh Bhasin ,  Kaushik Saha

IPC: G06K9/36 ,  G06K9/46 ,  G06T9/00 ,  H03M7/40 ,  H04N19/44 ,  H04N19/436 ,  H04N19/46 ,  H04N19/91

CPC classification number: G06T9/005 ,  H03M7/40 ,  H04N19/436 ,  H04N19/44 ,  H04N19/46 ,  H04N19/91

Abstract: Parallelization of decoding of a data stream encoded with a variable length code includes determining one or more markers, each of which indicates a position within the encoded data stream. The determined markers are included into the encoded data stream together with the encoded data. At the decoder side, the markers are parsed from the encoded data stream and based on the extracted markers. The encoded data is separated into partitions, which are decoded separately and in parallel.

Abstract translation: 用可变长度码编码的数据流的解码的并行化包括确定一个或多个标记，每个标记表示编码数据流内的位置。 所确定的标记与编码数据一起被包括在编码数据流中。 在解码器侧，从编码数据流中解析出标记，并根据提取的标记进行解析。 编码数据被分成分开并且并行解码的分区。

公开(公告)号：US20150002197A1

公开(公告)日：2015-01-01

申请号：US14046041

申请日：2013-10-04

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics (CROLLES 2) SAS

Inventor： Kallol CHATTERJEE ,  Nitin AGARWAL ,  Junaid YOUSUF ,  Nitin GUPTA ,  Pierre DAUTRICHE

IPC: H03L7/095

CPC classification number: H03L7/095

Abstract: A variable frequency clock generator. In aspects, a clock generator includes a droop detector circuit configured to monitor a voltage supply to an integrated circuit. If the supply voltage falls below a specific threshold, a droop voltage flag may be set such that a frequency-locked loop is triggered into a droop voltage mode for handling the voltage droop at the supply voltage. In response, a current control signal that is input to an oscillator that generates a system clock signal is reduced by sinking current away from the current control signal to the oscillator. This results in an immediate reduction on the system clock frequency. Such a state remains until the voltage droop has dissipated when the current path is removed for sinking some of the current.

Abstract translation: 变频时钟发生器。 在方面中，时钟发生器包括下垂检测器电路，其被配置为监视对集成电路的电压供应。 如果电源电压低于特定阈值，则可以设置下降电压标志，使得频率锁定环路被触发到用于处理电源电压的电压下降的下降电压模式。 作为响应，通过将电流从电流控制信号吸收到振荡器来减小输入到产生系统时钟信号的振荡器的电流控制信号。 这将立即降低系统时钟频率。 当去除电流路径以吸收一些电流时，这种状态保持直到电压下降消散。